Analog to digital conversion architecture and method with input and reference voltage scaling

ABSTRACT

An analog-to-digital converter stage includes: a comparator and logic circuit having first upper and lower unscaled voltage trip points that are different than upper and lower residue voltage trip points; and a switched capacitor circuit. The comparator and logic circuit is configured prior to an initial residue calculation cycle to compare a magnitude of an unscaled input voltage to the first upper and lower unscaled voltage trip points, to generate an initial output bit, and to generate a voltage scaling and gain control signal. The switched capacitor circuit is configured to sample the unscaled input voltage, to receive a reference voltage, and to receive the voltage scaling and gain control signal for selectively controlling a subset of switches of the switched capacitor circuit to scale the unscaled input voltage sample and reference voltage and generate an initial residue voltage during a single operation of the initial residue calculation cycle.

FIELD

The present disclosure relates generally to analog-to-digital conversionand more particularly to an analog-to-digital conversion architectureand method that provides for input voltage and reference voltagescaling.

BACKGROUND

Digital signal processing has been proven to be very efficient inhandling and manipulating large quantities of data. There are manyproducts that are in common use such as wireless devices, digitalcameras, motor controllers, automobiles, and toys, to name a few, thatrely on digital signal processing to operate. Many of these productscontinuously receive information such as light intensity, temperature,revolutions per minute, air pressure, and power, for example, which ismonitored and used to produce adjustments to the system, therebymaintaining optimum performance. This monitored information is often inthe form of an analog signal that must be converted to a representativedigital signal. An analog-to-digital converter (ADC) is used to convertthe analog signal to the digital signal. In general, theanalog-to-digital conversion process comprises periodically sampling theanalog signal and converting each sampled signal to a correspondingdigital signal.

Many products require ADCs to have the capability of handling bothsingle ended rail-to-rail inputs (e.g., a single signal representing avoltage) and differential rail-to-rail inputs (e.g., complementarysignals representing the same voltage). Also, due to pin limitations,the reference voltage used by the ADC may be derived from a main powersupply (e.g., V_(DDA), V_(SSA)). To satisfy these requirements, existingADCs contain a separate configurable block that scales and converts thevoltage and reference inputs to the desired differential levels and thenprovides the scaled analog input voltage to a redundant signed digit(RSD) analog-to-digital converter stage to perform an initial residuecalculation operation. The presence of this separate scaling processconsumes area as well as power.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying figures, where like reference numerals refer toidentical or functionally similar elements throughout the separateviews, together with the detailed description below, are incorporated inand form part of the specification, and serve to further illustrateembodiments of concepts that include the claimed invention, and explainvarious principles and advantages of those embodiments.

FIG. 1 is a circuit diagram illustrating a portion of ananalog-to-digital converter having an ADC stage performing input voltagescaling and an initial residue voltage calculation in the sameoperation, in accordance with an embodiment.

FIG. 2 is a circuit diagram illustrating a portion of ananalog-to-digital converter having an ADC stage performing input voltagescaling and an initial residue voltage calculation in the sameoperation, in accordance with another embodiment.

FIG. 3 is a circuit diagram illustrating a portion of ananalog-to-digital converter having an ADC stage performing input voltagescaling and an initial residue voltage calculation in the sameoperation, in accordance with another embodiment.

FIG. 4 is a circuit diagram illustrating an analog-to-digital converterhaving an ADC stage performing input voltage scaling and an initialresidue voltage calculation in the same operation, in accordance withanother embodiment.

FIG. 5 is a diagram depicting comparator trip points for unscaled singleended and differential input voltages processed using theanalog-to-digital converters shown in FIG. 1 to FIG. 4, in accordancewith an embodiment.

FIG. 6 is a circuit diagram illustrating an analog-to-digital converterhaving an ADC stage performing input voltage and reference voltagescaling and an initial residue voltage calculation in the sameoperation, in accordance with an embodiment.

FIG. 7 is a circuit diagram illustrating an analog-to-digital converterhaving an ADC stage performing input voltage and reference voltagescaling and an initial residue voltage calculation in the sameoperation, in accordance with another embodiment.

FIG. 8 is a circuit diagram illustrating an analog-to-digital converterhaving an ADC stage performing input voltage and reference voltagescaling and an initial residue voltage calculation in the sameoperation, in accordance with another embodiment.

FIG. 9 is a circuit diagram illustrating an analog-to-digital converterhaving an ADC stage performing input voltage and reference voltagescaling and an initial residue voltage calculation in the sameoperation, in accordance with another embodiment.

FIG. 10 is a diagram depicting comparator trip points for unscaledsingle ended and differential input voltages processed using theanalog-to-digital converters shown in FIG. 6 to FIG. 9, in accordancewith an embodiment.

FIG. 11 is a flow diagram illustrating a method implemented in an ADCstage, in accordance with an embodiment.

FIG. 12 is a diagram illustrating a comparator and logic circuit andcontroller that can be implemented by an ADC stage, in accordance withsome embodiments.

The present invention is illustrated by way of example and is notlimited by the accompanying figures, in which like references indicatesimilar elements. Skilled artisans will appreciate that elements in thefigures are illustrated for simplicity and clarity and have notnecessarily been drawn to scale. For example, the dimensions of some ofthe elements in the figures may be exaggerated relative to otherelements to help improve the understanding of embodiments of the presentinvention.

The apparatus and method components have been represented whereappropriate by conventional symbols in the drawings, showing only thosespecific details that are pertinent to understanding the embodiments ofthe present invention so as not to obscure the disclosure with detailsthat will be readily apparent to those of ordinary skill in the arthaving the benefit of the description herein.

DETAILED DESCRIPTION

In accordance with an embodiment, an analog-to-digital converter (ADC)stage comprises: a comparator and logic circuit configured with upperand lower unscaled voltage trip points; and a switched capacitor circuitcoupled to the comparator and logic circuit. The comparator and logiccircuit is configured, prior to an initial residue calculation cycle, tocompare a magnitude of an unscaled input voltage to the upper and lowerunscaled voltage trip points, to generate an initial output bitcorresponding to the magnitude of the unscaled input voltage, and togenerate a voltage scaling and gain control signal for use in theinitial residue calculation cycle. The switched capacitor circuitcomprises of a first voltage input, a voltage output, and a plurality ofcoupled capacitors and switches configured to sample the unscaled inputvoltage at the first voltage input to generate an unscaled input voltagesample and to receive the voltage scaling and gain control signal forselectively controlling a subset of the switches in order to scale theunscaled input voltage sample and generate an initial residue voltagehaving an initial residue magnitude at the voltage output during theinitial residue calculation cycle.

In accordance with a further embodiment, the comparator and logiccircuit is configured with upper and lower residue voltage trip points,which are different than the upper and lower unscaled voltage trippoints and is further configured, after the initial residue calculationcycle, to compare a magnitude of a residue voltage at the voltage input(which can be, for instance, the initial residue voltage or a residuevoltage from a different ADC stage) to the upper and lower residuevoltage trip points, to generate a next output bit corresponding to themagnitude of the residue voltage at the voltage input, and to generate again control signal; and wherein the switched capacitor circuit isfurther configured to receive the residue voltage at the voltage inputand the gain control signal and to generate a next residue voltageduring a next residue calculation cycle. In accordance with yet afurther embodiment, the switched capacitor circuit further comprises asecond voltage input, coupled to some of the switches, for receiving areference voltage, wherein the plurality of coupled capacitors andswitches is configured to scale the reference voltage while scaling theunscaled input voltage sample and while generating the initial residuevoltage during the initial residue calculation cycle.

Thus, the described embodiments of the present disclosure integrateinput scaling (and in some embodiments reference scaling) and an initialresidue calculation into one (i.e., the same) initial residuecalculation cycle, thereby, reducing both processing time and extracircuitry. The disclosed embodiments have the capability of handlingboth single ended and differential rail-to-rail input signals (e.g.,voltages). Moreover, the embodiments that integrate only the inputscaling and the initial residue calculation into the same operation(i.e., into the initial residue calculation cycle) can be incorporatedinto both pipelined ADCs and cyclic ADCs. However, some embodiments thatintegrate the input scaling, the reference scaling, and the initialresidue calculation into the same operation are more suitable forincorporating into cyclic ADCs. This is because the pipelined ADCstypically operate at a much higher speed (e.g., 10-100 times) than thecyclic ADCs, and A_(VDD) current in the pipelined ADCs is typicallyseveral orders of magnitude higher than in the cyclic ADCs. Therefore,switched capacitor-based reference voltages, which include transientglitches and high frequency switching noise due to repeated charging anddischarging operations, could adversely impact the operation of thepipelined ADC in some embodiments.

For the sake of brevity, conventional techniques related to switchedcapacitor circuits, ADC architectures, voltage comparator circuits,logic circuits, and other functional aspects of the system (and theindividual system operating components) may not be described in detail.Furthermore, the connecting lines shown in the various figures containedherein are intended to represent example functional relationships and/orphysical couplings between the various elements. It should be noted thatmany alternative or additional functional relationships or physicalconnections may be present in a practical embodiment. In addition, forease of discussion, where the figures illustrate example single endedimplementations, those skilled in the art can adapt illustratedtechniques for use in differential signaling applications using theprovided guidelines without departing from the scope of the presentdisclosure.

FIG. 1 is a circuit diagram illustrating a portion of ananalog-to-digital converter (ADC) 100 having: an initialanalog-to-digital converter stage 120 (also referred to herein as aconverter stage and an ADC stage) performing input voltage scaling andan initial residue voltage calculation in the same operation, inaccordance with an embodiment; and a second ADC stage 130. The ADC stage120 operates on an unscaled analog input voltage that comprises a singleended input voltage during the initial residue calculation cycle. In anembodiment, ADC stages 120 and 130 comprise the first two stages of apipelined ADC 100. However, in an alternate embodiment, ADC stage 120can be modified so that the ADC 100 is arranged to function as a cyclicADC, for example by employing similar circuit modifications asillustrated and described below by reference to FIG. 4. In such a case,the ADC stage 120 functions in accordance with the present teachingsduring the initial residue calculation cycle and thereafter functions,for instance, like the ADC stage 130 until the unscaled analog voltageis next sampled. Such a reconfigurable ADC stage 120 can be implementedin a cyclic ADC with the ADC stage 120 as the only stage in oneembodiment or in a two-stage cyclic ADC that includes the ADC stage 120and the ADC stage 130 in an alternate embodiment.

Turning now to the details of the ADC 100 as illustrated in FIG. 1, ADCstage 120 includes a first comparator and logic circuit 112 and a firstswitched capacitor circuit 122 coupled to the comparator and logiccircuit 112 at a voltage input (labeled as Vin) of the switchedcapacitor circuit 122. In accordance with the present teachings, thecomparator and logic circuit 112 is configured with upper and lowerunscaled voltage trip points (V_(H) and V_(L)) and is furtherconfigured, prior to an initial residue calculation cycle, to compare amagnitude of an unscaled input voltage (Vin) to the upper and lowerunscaled voltage trip points (V_(H) and V_(L)), to generate at least aninitial output bit (Dout) corresponding to the magnitude of the unscaledinput voltage Vin, and to generate a voltage scaling and gain controlsignal (h, m, or l). Further in accordance with the present teachings,the switched capacitor circuit 122 is configured to receive the unscaledinput voltage Vin and the voltage scaling and gain control signal (h, m,or l) and to generate an initial residue voltage (Vout) having aninitial residue magnitude during the initial residue calculation cycle.

ADC stage 130 includes a second comparator and logic circuit 134 and asecond switched capacitor circuit 132 coupled to the comparator andlogic circuit 134 at an output (labeled as Vout) of the switchedcapacitor circuit 122. The ADC stage 130 is any suitable ADC stage knownin the art, for example an ADC stage having a known RSD architecture(e.g., a 1.5 bit RSD stage, explained in more detail later), whichperforms a residue calculation without scaling the voltage received atthe input of the RSD stage. The comparator and logic circuit 134 isconfigured with upper and lower residue voltage trip points (not shownin FIG. 1 but an example of which is shown in FIG. 5), which aredifferent than the upper and lower unscaled voltage trip points (V_(H)and V_(L)). Different upper and lower trip points means that at leastone of the trip points (the upper trip point or the lower trip point)has changed or is different, although in the disclosed embodiments boththe upper and lower trip points are different. The comparator and logiccircuit 134 is further configured to compare the magnitude of Vout tothe upper and lower residue voltage trip points to generate at least asecond output bit (Dout2) corresponding to the magnitude of Vout and togenerate a first gain control signal (h2, m2, or l2). The secondswitched capacitor circuit 132 is configured to receive the initialresidue voltage (Vout) and the first gain control signal (h2, m2, or l2)and to generate a second residue voltage (V_(out2)) during a secondresidue calculation cycle, which is provided to a next ADC stage (notshown) of the pipelined ADC 100.

A general description is first provided of an ADC comprising an ADCstage in accordance with the present teachings, including anintroduction and description of relevant terminology used throughoutthis disclosure. In some embodiments, the ADC includes a plurality ofADC stages having an initial stage in accordance with the presentteachings, for instance in accordance with any of the embodimentsillustrated by reference to FIG. 1-4 or 6-9. In alternate embodiments,the ADC includes only a single ADC stage implemented in accordance withthe present teachings. Resolution or accuracy of the ADC is a functionof the resolution of each individual stage and the number (N) of bits,of a digital word, generated during a process of converting a sample ofan unscaled analog signal (also referred to herein as an unscaled inputvoltage) to a representative digital signal. The unscaled input voltagecomprises a parameter that is being monitored and for which periodicsamples are taken and converted to the representative digital signalusing the ADC. The frequency at which each sample of the unscaled inputvoltage is taken and correspondingly converted into a digital word iscontrolled by a main clock signal for the ADC.

Each ADC stage provides at least one bit of the N-bit ADC resolution,starting with the most significant bit (MSB), e.g., Dout, (also referredto herein as an initial output bit) generated by the comparator andlogic circuit of an initial ADC stage, proceeding with a sequence (i.e.,two or more) of bits generated by subsequent ADC stages in a pipelinedADC or by the same ADC stage(s) during subsequent residue calculationcycles in a cyclic ADC, and ending with a least significant bit (LSB)from a last or final ADC stage (or residue calculation cycle)implemented in the ADC. Accordingly, the term analog-to-digitalconversion process (also referred to herein as an ADC process) refers toone complete cycle of analog-to-digital conversion whereby one sample ofan unscaled analog voltage is taken or obtained and converted to asequence of N bits beginning with the MSB and ending with the LSB.

As used here, the term “initial” means first in a sequence (although theconverse is not true, i.e., the use herein of the term “first” does notnecessarily imply relative position, unless otherwise stated). Thus, aninitial residue calculation cycle is the first residue calculation cyclein a sequence of residue calculation cycles of an analog-to-digitalconversion process; and a next or subsequent residue calculation cyclerefers to any of the remaining residue calculation cycles of thesequence. An initial residue voltage is the first residue voltage of asequence of residue voltages generated during the analog-to-digitalconversion process; and a next or subsequent residue voltage refers toany of the remaining residue voltages of the sequence. An initial outputbit is the first output bit of a sequence of output bits generatedduring the analog-to-digital conversion process; and a next orsubsequent output bit refers to any of the remaining output bits of thesequence.

Turning back to the detailed description of the ADC stage 120 of FIG. 1,as mentioned above, ADC stage 120 is the initial ADC stage of the ADC100. The initial ADC stage is the ADC stage that performs the initialresidue calculation cycle of a sequence of residue calculation cyclesfor an analog-to-digital conversion process, wherein a residuecalculation cycle is the switched capacitor circuit operation thatgenerates or produces a residue voltage at the output of the ADC stage(e.g., labeled as Vout at a node N104). The comparator and logic circuit112 of the ADC stage 120 comprises: a comparator 114 implemented as anoperational amplifier configured with an upper voltage trip point V_(H)at an inverting input and a non-inverting input coupled to the firstvoltage input (Vin); a comparator 116 implemented as an operationalamplifier configured with a lower voltage trip point V_(L) at aninverting input and a non-inverting input coupled to the first voltageinput (Vin); and a logic circuit 118 coupled to outputs of thecomparators 114 and 116.

During operation, in general, when an analog voltage having anassociated magnitude appears at the first voltage input of the switchedcapacitor circuit of the initial ADC stage (e.g., 120), the comparatorand logic circuit 112 compares the magnitude of the analog input voltageagainst at least one of the voltage trip points V_(H) and V_(L) andgenerates a corresponding logic level (e.g., −1, 1, or 0). The logiclevel determines a digital output bit (e.g., Dout) for the ADC stage 120and correspondingly sets a control signal (h, m, or l) used toselectively close one or more gain control switch(s) of the switchedcapacitor circuit 122, in order to produce a corresponding analogremainder voltage (referred to herein as a residue voltage) at theoutput labeled Vout. As used herein, a residue voltage is the remainderof the analog input voltage less the value of the logic bit produced bythe comparator and logic circuit. More particularly, when the magnitudeof the analog input voltage is larger than V_(H), the logic circuit 118sets the control signal to h, and the gain control switch(s) controlledby the control signal h are closed during the following residuecalculation cycle. When the magnitude of the analog input voltage isbetween V_(L) and V_(H), the logic circuit 118 sets the control signalto m, and the gain control switch(s) controlled by the control signal mare closed during the following residue calculation cycle. When themagnitude of the analog input voltage is less than V_(L), the logiccircuit 118 sets the control signal to l, and the gain control switch(s)controlled by the control signal l are closed during the followingresidue calculation cycle.

In accordance with the teachings herein, the comparator and logiccircuit 112 is configured with upper and lower voltage trip points thatare different than the upper and lower trip points used by thecomparator and logic circuit 134. More particularly, prior to theinitial residue calculation cycle (which is performed by the switchedcapacitor circuit 122), the upper and lower voltage trip points of thecomparator and logic circuit 112 comprise upper and lower unscaledvoltage trip points (V_(H) and V_(L)), which are compared to themagnitude of an unscaled input voltage. The unscaled input voltage is ananalog input voltage having a magnitude (or value) that can swing fromrail-to-rail. Such a voltage must be scaled to the operating range of anoperational amplifier 102 within the switched capacitor circuit 122.However, after the initial residue calculation cycle, the upper andlower voltage trip points used by the comparator and logic circuit 134(and used until the next unscaled input voltage sample is taken)comprises upper and lower residue voltage trip points, which aredifferent than the upper and lower unscaled voltage trip points. Theupper and lower residue voltage trip points are compared to themagnitude of the residue voltage Vout generated by the preceding ADCstage 122, which appears at the input of the ADC stage 130. The residuevoltage Vout has a residue magnitude that falls within the operatingrange of an operational amplifier within the switched capacitor circuit132 (not shown), and thus generally requires no scaling.

Accordingly, at the beginning of an ADC process during a first period ofthe main clock signal for the ADC 100, the comparator and logic circuit112 is configured, prior to the initial residue calculation cycle, tocompare a magnitude of an unscaled input voltage (at Vin) to the firstupper V_(H) and lower V_(L) unscaled voltage trip points using thecomparators 114 and 116. The results of the comparison are fed to thelogic circuit 118, which uses the results to generate an initial outputbit (Dout) corresponding to the magnitude of the unscaled input voltage,and to generate a voltage scaling and gain control signal (h, m, l) foruse in the initial residue calculation cycle. It should be noted thatonly the control signal generated prior to the initial residuecalculation cycle is referred to herein as the “voltage scaling and gaincontrol signal”, and all other control signals generated after theinitial residue calculation cycle are referred to herein simply as “gaincontrol signals.”

Turning momentarily to FIG. 5, shown therein are diagrams 500, 510, and520 depicting example values for upper and lower voltage trip pointsets. In one embodiment, the comparator and logic circuit 112 isconfigured with first upper and lower unscaled voltage trip pointshaving values (V_(H)=5/4vref and V_(L)=¾vref from a range of 0 to 2vref)shown in diagram 500, to process a single ended input voltage prior tothe initial residue calculation cycle. Vref is a reference voltageprovided to the switched capacitor circuit of the ADC stages. Bycontrast, the comparator and logic circuit 134 is configured with upperand lower residue voltage trip points having values (V_(H)=¼vref andV_(L)=−¼vref from a range of −vref to vref) shown in diagram 520, toprocess the initial residue voltage Vout.

Turning again to the description of the ADC 100 of FIG. 1, the switchedcapacitor circuit 122 further includes: a second voltage input (labeledas vref) for receiving a reference voltage; a voltage supply node N100(which is coupled to a common mode voltage V_(CM) (also referred to inthe art as a voltage common mode or AC ground), which in someimplementations is a voltage that is approximately in the middle of theoperating range of the operational amplifier 102; a voltage output(which is the output Vout of the ADC stage 120 at the node N104); aplurality of coupled switches and capacitors, with the connectivity ofthese elements described below; and the operational amplifier 102 havingan inverting input coupled to (“at”) the node N100, a non-invertinginput at a node N102, and an output terminal coupled to (and serving as)the voltage output (Vout) of the switched capacitor circuit 120, at thenode N104. The plurality of coupled capacitors comprises four capacitors104, 106, 108, and 110 each having a same capacitance value and eachhaving first and second terminals. As shown, all four capacitors have afirst terminal coupled together at a node N106. The second terminal ofthe capacitor 104 is coupled to a node N108. The second terminal of thecapacitor 106 is coupled to a node N110. The second terminal of thecapacitor 108 is coupled to a node N112. The second terminal of thecapacitor 110 is coupled to a node N114.

The plurality of coupled switches comprises a first set of switches(S100, S102, S104, S106, and S108) coupled to the first voltage input(Vin), the voltage supply node N100 and the four capacitors 104-110. Theremainder of the plurality of coupled switches comprises a second set ofswitches (S110, S112, S114, S116, S118, S120, and S122) that includes asubset of the switches (S116, S118, S120, and S122) that are selectivelycontrolled by the voltage scaling and gain control signal (h, m, l)provided by the comparator and logic circuit 112. Selectivelycontrolling (also referred to herein as selectively closing) the subsetof switches means that only selected ones of the subset of switches areclosed during the residue calculation cycle depending on which controlsignal h, m, or l is output from the logic circuit. The second set ofswitches (S110-S122) is coupled to the second voltage input (vref), thevoltage supply node N100, the four capacitors 104-110, and thenon-inverting input at node N102 and the output (at Vout) of theoperational amplifier 102. Each switch has at least first and secondterminals and can be implemented using any suitable transistortechnology including, but not limited to, MOSFET (metal oxidesemiconductor field effect transistor) technology.

The connectivity of the switches within this illustrative switchedcapacitor circuit 122 is as follows. The first terminal of switch S100is coupled to the first voltage input (Vin), and the second terminal iscoupled to the node N108. The first terminal of switch S102 is coupledto the first voltage input (Vin), and the second terminal is coupled tothe node N110. The first terminal of switch S104 is coupled to thevoltage supply node, and the second terminal is coupled to the nodeN112. The first terminal of switch S106 is coupled to the voltage supplynode, and the second terminal is coupled to the node N114. The firstterminal of switch S108 is coupled to the voltage supply node, and thesecond terminal is coupled to the node N106. The first terminal ofswitch S110 is coupled to the node N108, and the second terminal iscoupled to the output of the operational amplifier 102 at the node N104.The first terminal of switch S112 is coupled to the node N106, and thesecond terminal is coupled to the non-inverting input of the operationalamplifier 102 at the node N102. The first terminal of switch S114 iscoupled to the second voltage input (vref), and the second terminal iscoupled to the node N110. The first terminal of switch S116 is coupledto the voltage supply node, and the second terminal is coupled to thenode N112. The first terminal of switch S118 is coupled to the secondvoltage input (vref), and the second terminal is coupled to the nodeN112. The first terminal of switch S120 is coupled to the voltage supplynode, and the second terminal is coupled to the node N114. The firstterminal of switch S122 is coupled to the second voltage input (vref),and the second terminal is coupled to the node N114.

Each of the plurality of coupled switches is further labeled by theirrespective governing clock signal (p1 or p2) or control signal (h, m, orl) that controls the opening and closing of the switch. Duringoperation, when a clock or control signal is “high”, the associatedswitch is closed; and when a clock or control signal is “low”, theassociated switch is open. More specifically, the first set of switchesS100-S108 (also referred to herein as sampling control switches) isgoverned by a sampling control clock signal p1. The second set ofswitches S110-S122 (also referred to herein as gain control switches) isgoverned by a gain control clock signal p2. The subset (S116-S122) ofthe switches is governed by control signals h, m, and l with: switchS116 being controlled to close by control signal l; switch S118 beingcontrolled to close by control signals h or m; switch S120 beingcontrolled to close by control signal l; and switch S122 beingcontrolled to close by control signal h.

As used herein, sampling control switches are switches that are or canbe closed using a requisite sampling control clock signal to configureor reconfigure the switched capacitor circuit during a sample (orsampling) cycle of the circuit. Gain control switches are switches thatare or can be closed using a requisite gain control clock signal toconfigure or reconfigure the switched capacitor circuit during a gaincycle of the circuit (also referred to herein as a residue calculationcycle). A sampling control clock signal refers to a family of periodicclock signals (that typically also includes a delayed and complementaryclock signal) derived from or associated with the main clock signal ofthe ADC and used to clock the sampling control switches during thesample cycle of a switched capacitor circuit. A gain control clocksignal refers to a family of periodic clock signals (that typically alsoincludes a delayed and complementary clock signal) derived from orassociated with the main clock signal of the ADC and used to clock thegain control switches during the residue calculation cycle of a switchedcapacitor circuit. The sampling control clock signal and the gaincontrol clock signal are non-overlapping with respect to each other. Twoclock signals are non-overlapping with respect to each other if only oneof the clock signals is high at any given time. In other words, if twonon-overlapping clock signals are viewed on the same time axis, therepetitive clock pulses of the respective signals never overlap and arealways separated, in time, from one another. Accordingly, the samplecycle and the residue calculation cycle of each ADC stage of the ADCalways occur at non-overlapping points in time.

During operation of the initial ADC stage 100, during the same mainclock period in which the comparator and digital circuit 112 generatesthe initial output bit, the first set of switches (S100-S108) isconfigured to close under the control of the sampling control clocksignal p1 during the sample cycle to charge the capacitors 104 and 106in order to sample an unscaled input voltage at the first voltage input(Vin), thereby generating an unscaled input voltage sample. Upon theconclusion of the sample cycle when control signal p1 controls the firstset of switches to open, the second set of switches (S110-S122) isconfigured to selectively close under the control of the gain controlclock signal p2 and the voltage scaling and gain control signal (h, m,or l), generated by the comparator and logic circuit 112 during theinitial main clock period that initiated the ADC process, to scale theunscaled input voltage sample and generate the initial residue voltagebased on the comparison of the magnitude of the unscaled input voltageto the first upper and lower unscaled voltage trip points (e.g., asshown in diagram 500 of FIG. 5).

In the illustrative circuit arrangement 120, during the initial residuecalculation phase and when the unscaled input voltage comprises a singleended input voltage, the switched capacitor circuit generates theinitial residue voltage at the node N104 having a magnitude determinedby and in accordance with the following set of equations:

$\begin{matrix}\begin{matrix}\begin{matrix}\underset{\_}{{when},{{Vin} > {Vh}}} \\{{{Vout} = {{2\left( {{Vin} - {vref}} \right)} - {vref}}};}\end{matrix} \\{{Vout} = {{2{Vin}} - {3{vref}}}}\end{matrix} & (1) \\\begin{matrix}\begin{matrix}\underset{\_}{{when},{{Vh} > {Vin} > {V\; 1}}} \\{{Vout} = {2\left( {{Vin} - {vref}} \right)}}\end{matrix} \\{{{Vout} = {{2{Vin}} - {3{vref}}}};}\end{matrix} & (2) \\\begin{matrix}\begin{matrix}\underset{\_}{{when},{{Vin} < {V\; 1}}} \\{{Vout} = {{2\left( {{Vin} - {vref}} \right)} + {vref}}}\end{matrix} \\{{{Vout} = {{2{Vin}} - {3{vref}}}},}\end{matrix} & (3)\end{matrix}$wherein Vin is the magnitude of the unscaled input voltage, Vout is theinitial residue magnitude, vref is a magnitude of the reference voltage,Vh (i.e., V_(H)) is the upper unscaled voltage trip point, and Vl (i.e.,V_(L)) is the lower unscaled voltage trip point. In the sets ofequations (1), (2), and (3), the magnitude (Vin) of the unscaled inputvoltage is scaled by (−2vref) to maintain the input voltage withinoperating range of the operational amplifier 102.

The residue voltage Vout is provided to the next ADC stage 130. In someembodiments, the ADC stage 130 is a known 1.5 bit RSD ADC stage, whichprovides a one bit logic output and 0.5 bit of redundancy, used fordigital correction to reduce comparator offset requirements.Accordingly, the comparator and logic circuit 134 also comprises twocomparators and a logic circuit that function in a similar manner as thecomparator and logic circuit 112, except that the upper and lowervoltage trip points are the upper and lower residue voltage trip pointwhich, for example, have the values shown in diagram 520 of FIG. 5. Theswitched capacitor circuit 132 comprises an operational amplifier, and aplurality of capacitors and switches coupled and configured to generateV_(out2) by multiplying Vout by a factor of two and then adding avoltage of vref, 0, or −vref depending on which control signal (h2, m2,or l2) the comparator and logic circuit 134 generates. Moreparticularly, Vin>Vh, Vout=2Vin−vref; when Vh>Vin>Vl, Vout=2Vin; andwhen Vin<Vl, Vout=2Vin+vref.

Turning now to FIG. 2, shown therein is a circuit diagram illustrating aportion of an ADC 200 having: an initial ADC stage 220 performing inputvoltage scaling and an initial residue voltage calculation in the sameoperation, in accordance with another embodiment; and a second ADC stage230. The ADC stage 220 operates on an unscaled analog input voltage thatcomprises a differential input voltage. In an embodiment, ADC stages 220and 230 comprise the first two stages of a pipelined ADC 200. However,in an alternate embodiment, ADC stage 220 can be modified so that theADC 200 is arranged to function as a cyclic ADC, for example byemploying similar circuit modifications as illustrated and describedbelow by reference to FIG. 4. In such a case, the ADC stage 220functions in accordance with the present teachings during the initialresidue calculation cycle and thereafter functions, for instance, likethe ADC stage 230 until the unscaled analog voltage is next sampled.Such a reconfigurable ADC stage 220 can be implemented in a cyclic ADCwith the ADC stage 220 as the only stage in one embodiment or in atwo-stage cyclic ADC that includes the ADC stage 220 and the ADC stage230 in an alternate embodiment.

ADC stage 220 includes a comparator and logic circuit (not shown in FIG.2) and a switched capacitor circuit 222 coupled to the comparator andlogic circuit at a first voltage input (labeled as Vin) of the switchedcapacitor circuit. The comparator and logic circuit of the ADC stage 220comprises two comparators and a logic circuit that function in a similarmanner as the comparator and logic circuit 112, except that the upperand lower voltage trip points are second upper and lower unscaledvoltage trip point that are different than the first upper and lowerunscaled voltage trip points used by the comparator and logic circuit112. The second upper and lower unscaled voltage trip points are usedwhen the unscaled input voltage comprises a differential voltage and, inone embodiment, have the values (V_(H)=−½ vref and V_(L)=½ vref from arange of −vref to vref) as shown in diagram 510 of FIG. 5.

The switched capacitor circuit 222 further: a second voltage input(labeled as vref) for receiving a reference voltage; a third voltageinput (labeled as −vref) for receiving a negative reference voltage; avoltage supply node N200 which is coupled to a common mode voltageV_(CM), which in some implementations is a voltage that is approximatelyin the middle of the operating range of the ADC stage 220; a voltageoutput (which is an output Vout of the ADC stage 220) at a node N204; aplurality of coupled switches and capacitors, with the connectivity ofthese elements described below; and an operational amplifier 202 havingan inverting input coupled to (“at”) the node N200, a non-invertinginput at a node N202, and an output terminal coupled to (and serving as)the voltage output (Vout) of the switched capacitor circuit, at the nodeN204. The plurality of coupled capacitors comprises four capacitors 204,206, 208, and 210 each having a same capacitance value and each havingfirst and second terminals. As shown, all four capacitors have a firstterminal coupled together at a node N206. The second terminal of thecapacitor 204 is coupled to a node N208. The second terminal of thecapacitor 206 is coupled to a node N210. The second terminal of thecapacitor 208 is coupled to a node N212. The second terminal of thecapacitor 210 is coupled to a node N214.

The plurality of coupled switches comprises a first set of switches(S200, S202, S204, S206, and S208) coupled to the first voltage input(Vin), the voltage supply node N200 and the four capacitors 204-210. Theremainder of the plurality of coupled switches comprises a second set ofswitches (S210, S212, S214, S216, S218, S220, S222, S224, and S226) thatincludes a subset of the switches (S216, S218, S220, S222, S224, andS226) that are selectively controlled by the voltage scaling and gaincontrol signal (h, m, l) provided by the comparator and logic circuit.The second set of switches (S210-S226) is coupled to the second voltageinput (vref), the third voltage input (−vref), the voltage supply nodeN200, the four capacitors 204-210, and the non-inverting input at nodeN202 and the output (at Vout) of the operational amplifier 202. Eachswitch has at least first and second terminals and can be implementedusing any suitable transistor technology including, but not limited to,MOSFET technology.

The connectivity of the switches within this illustrative switchedcapacitor circuit is as follows. The first terminal of switch S200 iscoupled to the first voltage input (Vin), and the second terminal iscoupled to the node N208. The first terminal of switch S202 is coupledto the first voltage input (Vin), and the second terminal is coupled tothe node N210. The first terminal of switch S204 is coupled to thevoltage supply node, and the second terminal is coupled to the nodeN212. The first terminal of switch S206 is coupled to the voltage supplynode, and the second terminal is coupled to the node N214. The firstterminal of switch S208 is coupled to the voltage supply node, and thesecond terminal is coupled to the node N206. The first terminal ofswitch S210 is coupled to the node N208, and the second terminal iscoupled to the output of the operational amplifier 202 at the node N204.The first terminal of switch S212 is coupled to the node N206, and thesecond terminal is coupled to the non-inverting input of the operationalamplifier 202 at the node N202. The first terminal of switch S214 iscoupled to the output (Vout), and the second terminal is coupled to thenode N210. The first terminal of switch S216 is coupled to the thirdvoltage input (−vref), and the second terminal is coupled to the nodeN212. The first terminal of switch S218 is coupled to the voltage supplynode, and the second terminal is coupled to the node N212. The firstterminal of switch S220 is coupled to the second voltage input (vref),and the second terminal is coupled to the node N212. The first terminalof switch S222 is coupled to the third voltage input (−vref), and thesecond terminal is coupled to the node N214. The first terminal ofswitch S224 is coupled to the voltage supply node, and the secondterminal is coupled to the node N214. The first terminal of switch S226is coupled to the second voltage input (vref), and the second terminalis coupled to the node N214.

Each of the plurality of coupled switches is further labeled by theirrespective governing clock signal (p1 or p2) or control signal (h, m, orl) that controls the opening and closing of the switch. Duringoperation, when a clock or control signal is “high”, the associatedswitch is closed; and when a clock or control signal is “low”, theassociated switch is open. More specifically, the first set of switchesS200-S208 (also referred to herein as sampling control switches) isgoverned by a sampling control clock signal p1. The second set ofswitches S210-S226 (also referred to herein as gain control switches) isgoverned by a gain control clock signal p2. The subset (S216-S226) ofthe switches is governed by control signals h, m, and l with: switchS216 being controlled to close by control signal l; switch S218 beingcontrolled to close by control signal m; switch S220 being controlled toclose by control signal h; and switch S222 being controlled to close bycontrol signal l; switch S224 being controlled to close by controlsignal m; and switch S226 being controlled to close by control signal h.

During operation of the initial ADC stage 220, during the same mainclock period in which the comparator and digital circuit generates theinitial output bit, the first set of switches (S200-S208) is configuredto close under the control of the sampling control clock signal p1during the sample cycle to charge the capacitors 204 and 206 in order tosample an unscaled input voltage at the first voltage input (Vin),thereby generating an unscaled input voltage sample. Upon the conclusionof the sample cycle when control signal p1 controls the first set ofswitches to open, the second set of switches (S210-S226) is configuredto selectively close under the control of the gain control clock signalp2 and the voltage scaling and gain control signal (h, m, or l),generated by the comparator and logic circuit during the initial mainclock period that initiated the ADC process, to scale the unscaled inputvoltage sample and generate the initial residue voltage based on thecomparison of the magnitude of the unscaled input voltage to the firstupper and lower unscaled voltage trip points (e.g., as shown in diagram510 of FIG. 5).

In the illustrative circuit arrangement 220, during the initial residuecalculation cycle and when the unscaled input voltage comprises adifferential input voltage, the switched capacitor circuit generates theinitial residue voltage at the node N204 having a magnitude determinedby and in accordance with the following sets of equations:

$\begin{matrix}\begin{matrix}\begin{matrix}\underset{\_}{{when},{{Vin} > {Vh}}} \\{{{Vout} = {{2\left( \frac{Vin}{2} \right)} - {vref}}};}\end{matrix} \\{{2{Vout}} = {{2{Vin}} - {2{vref}}}}\end{matrix} & (4) \\\begin{matrix}\begin{matrix}\underset{\_}{{when},{{Vh} > {Vin} > {V\; 1}}} \\{{{Vout} = {2\left( \frac{Vin}{2} \right)}};}\end{matrix} \\{{2{Vout}} = {2{Vin}}}\end{matrix} & (5) \\\begin{matrix}\begin{matrix}\underset{\_}{{when},{{Vin} < {V\; 1}}} \\{{{Vout} = {{2\left( \frac{Vin}{2} \right)} + {vref}}},}\end{matrix} \\{{2{Vout}} = {{2{Vin}} + {2{vref}}}}\end{matrix} & (6)\end{matrix}$wherein Vin is the magnitude of the unscaled input voltage, Vout is theinitial residue magnitude, vref is a magnitude of the reference voltage,Vh is the upper unscaled voltage trip point, and Vl is the lowerunscaled voltage trip point. In the sets of equations (4), (5), and (6),the magnitude (Vin) of the unscaled input voltage is scaled by (½) tomaintain the input voltage within operating range of the operationalamplifier 202. The residue voltage Vout is provided to the next ADCstage 230, which in some embodiments is a 1.5 bit RSD ADC stage. In thisillustrative pipelined ADC implementation, the ADC stage 230 provides aresidue voltage V_(out2) to the next ADC stage (not shown).

Turning now to FIG. 3, shown therein is a circuit diagram illustrating aportion of an ADC 300 having: an initial ADC stage 320 performing inputvoltage scaling and an initial residue voltage calculation in the sameoperation, in accordance with another embodiment; and a second ADC stage330. The ADC stage 320 operates on an unscaled analog input voltage thatcomprises either a single ended input voltage or a differential inputvoltage. In an embodiment, ADC stages 320 and 330 comprise the first twostages of a pipelined ADC 300. However, in an alternate embodiment, ADCstage 320 can be modified so that the ADC 300 is arranged to function asa cyclic ADC, for example by employing similar circuit modifications asillustrated and described below by reference to FIG. 4. In such a case,the ADC stage 320 functions in accordance with the present teachingsduring the initial residue calculation cycle and thereafter functions,for instance, like the ADC stage 330 until the unscaled analog voltageis next sampled. Such a reconfigurable ADC stage 320 can be implementedin a cyclic ADC with the ADC stage 320 as the only stage in oneembodiment or in a two-stage cyclic ADC that includes the ADC stage 320and the ADC stage 330 in an alternate embodiment.

ADC stage 320 includes a comparator and logic circuit (not shown in FIG.3) and a switched capacitor circuit 322 coupled to the comparator andlogic circuit at a first voltage input (labeled as Vin) of the switchedcapacitor circuit. In an embodiment, the comparator and logic circuit ofthe ADC stage 320 is configured as a comparator and logic circuit 1200shown in FIG. 12. The comparator and logic circuit 1200 includes acomparator 1206, a comparator 1208, and a logic circuit 1204. Thecomparator 1206 is implemented as an operational amplifier having: anon-inverting input coupled to receive an analog input voltage (e.g.,the unscaled input voltage Vin in a pipelined ADC arrangement and aresidue voltage Vout in a cyclic ADC arrangement); an inverting inputcoupled to multiple upper unscaled voltage trip points, V_(HS) andV_(HD); and an output coupled to the logic circuit 1204. The comparator1208 is implemented as an operational amplifier having: a non-invertinginput coupled to receive the analog input voltage; an inverting inputcoupled to multiple lower unscaled voltage trip points, V_(LS) andV_(LD); and an output coupled to the logic circuit 1204.

As implemented in the ADC stage 320 (of FIG. 3), when the ADC 300 is apipelined ADC, the inverting input of the comparator 1206 is coupled toV_(HS) using a switch S1200 and to V_(HD) using a switch 1202; and theinverting input of the comparator 1208 is coupled to V_(LS) using aswitch S1206 and to V_(LD) using a switch 1208. Accordingly, prior tothe initial residue calculation cycle, the comparator and logic circuit1200 is configured with first upper (V_(HS)) and lower (V_(Ls)) unscaledvoltage trip points when the unscaled input voltage Vin is asingle-ended voltage and is configured with second upper (V_(HD)) andlower (V_(LD)) unscaled voltage trip points when the unscaled inputvoltage Vin is a differential voltage. In an embodiment, the first upper(V_(HS)) and lower (V_(Ls)) unscaled voltage trip points have the valuesillustrated in diagram 500 of FIG. 5, and the second upper (V_(HD)) andlower (V_(LD)) unscaled voltage trip points have the values illustratedin diagram 510 of FIG. 5. As implemented in the ADC stage 320 (of FIG.3), when the ADC 300 is a cyclic ADC, the inverting input of thecomparator 1206 is further coupled to an upper residue voltage trippoint V_(HR) using a switch S1204, and the inverting input of thecomparator 1208 is further coupled to a lower residue voltage trip pointV_(LR) using a switch S1210. In an embodiment, the upper (V_(HR)) andlower (V_(LR)) unscaled voltage trip points have the values illustratedin diagram 520 of FIG. 5.

The closing of the switches S1200, S1202, S1204, S1206, S1208, and S1210is controlled by control signals C_(S), C_(D) and C_(R) provided by afinite state machine 1202 of the ADC. More particularly, a controller(not shown) of the ADC controls the finite state machine 1202 to:generate the control signal C_(S) when the analog input voltage is asingle-ended input voltage signal; generate the control signal C_(D)when the analog input signal is a differential input voltage signal; andgenerate the control signal C_(R) when the analog input voltage is aresidue voltage. Once the appropriate upper and lower unscaled voltagetrip points are connected to the comparators 1206 and 1208, thecomparator and logic circuit 1200 functions in the same manner as thecomparator and logic circuit 112 (of FIG. 1) to compare the magnitude ofthe input voltage to the upper and lower voltage trip points to generatean output bit Dout and a voltage scaling and gain control signal (or again control signal) h, m, or l depending on the results of thecomparison.

Returning to the description of FIG. 3, the switched capacitor circuit322 further includes: a second voltage input (labeled as vref) forreceiving a reference voltage; a third voltage input (labeled as −vref)for receiving a negative reference voltage; a voltage supply node N300which is coupled to a common mode voltage V_(CM), which in someimplementations is a voltage that is approximately in the middle of theoperating range of the ADC stage 320; a voltage output (which is anoutput Vout of the ADC stage 320) at a node N304; a plurality of coupledswitches and capacitors, with the connectivity of these elementsdescribed below; and an operational amplifier 302 having an invertinginput coupled to (“at”) the node N300, a non-inverting input at a nodeN302, and an output terminal coupled to (and serving as) the voltageoutput (Vout) of the switched capacitor circuit, at the node N304. Theplurality of coupled capacitors comprises four capacitors 304, 306, 308,and 310 each having a same capacitance value and each having first andsecond terminals. As shown, all four capacitors have a first terminalcoupled together at a node N306. The second terminal of the capacitor304 is coupled to a node N308. The second terminal of the capacitor 306is coupled to a node N310. The second terminal of the capacitor 308 iscoupled to a node N312. The second terminal of the capacitor 310 iscoupled to a node N314.

The plurality of coupled switches comprises a first set of switches(S300, S302, S304, S306, and S308) coupled to the first voltage input(Vin), the voltage supply node N300 and the four capacitors 304-310. Theremainder of the plurality of coupled switches comprises a second set ofswitches (S310, S312, S314, S316, S318, S320, S322, S324, S326, andS328) that includes a subset of the switches (S318, S320, S322, S324,S326, and S328) that are selectively controlled by the voltage scalingand gain control signal (h, m, l) provided by the comparator and logiccircuit 1200 and at least the control signals C_(S) and C_(D) providedby the finite state machine 1202. The second set of switches (S310-S328)is coupled to the second voltage input (vref), the third voltage input(−vref), the voltage supply node N300, the four capacitors 304-310, andthe non-inverting input at node N302 and the output (at Vout) of theoperational amplifier 302. Each switch has at least first and secondterminals and can be implemented using any suitable transistortechnology including, but not limited to, MOSFET technology.

The connectivity of the switches within this illustrative switchedcapacitor circuit is as follows. The first terminal of switch S300 iscoupled to the first voltage input (Vin), and the second terminal iscoupled to the node N308. The first terminal of switch S302 is coupledto the first voltage input (Vin), and the second terminal is coupled tothe node N310. The first terminal of switch S304 is coupled to thevoltage supply node, and the second terminal is coupled to the nodeN312. The first terminal of switch S306 is coupled to the voltage supplynode, and the second terminal is coupled to the node N314. The firstterminal of switch S308 is coupled to the voltage supply node, and thesecond terminal is coupled to the node N306. The first terminal ofswitch S310 is coupled to the node N308, and the second terminal iscoupled to the output of the operational amplifier 302 at the node N304.The first terminal of switch S312 is coupled to the node N306, and thesecond terminal is coupled to the non-inverting input of the operationalamplifier 302 at the node N302. The first terminal of switch S314 iscoupled to the output (Vout), and the second terminal is coupled to thenode N310. The first terminal of switch S316 is coupled to the secondvoltage input (vref), and the second terminal is coupled to the nodeN310. The first terminal of switch S318 is coupled to the third voltageinput (−vref), and the second terminal is coupled to the node N312. Thefirst terminal of switch S320 is coupled to the voltage supply node, andthe second terminal is coupled to the node N312. The first terminal ofswitch S322 is coupled to the second voltage input (vref), and thesecond terminal is coupled to the node N312. The first terminal ofswitch S324 is coupled to the third voltage input (−vref), and thesecond terminal is coupled to the node N314. The first terminal ofswitch S326 is coupled to the voltage supply node, and the secondterminal is coupled to the node N314. The first terminal of switch S328is coupled to the second voltage input (vref), and the second terminalis coupled to the node N314.

Each of the plurality of coupled switches is further labeled by theirrespective governing clock signal (p1 or p2) or control signal (h, m, orl) that controls the opening and closing of the switch. Duringoperation, when a clock or control signal is “high”, the associatedswitch is closed; and when a clock or control signal is “low”, theassociated switch is open. More specifically, the first set of switchesS300-S308 (also referred to herein as sampling control switches) isgoverned by a sampling control clock signal p1. The second set ofswitches S310-S328 (also referred to herein as gain control switches) isgoverned by a gain control clock signal p2. In addition, the gaincontrol switches may be labeled with an “S” or “D”. More particularly, again control switch labeled with only an “S” is controlled to close onlywhen the control signal C_(S) (FIG. 12) is high and is used only whenoperating on a single ended input voltage. A gain control switch labeledwith only a “D” is controlled to close only when the control signalC_(D) (FIG. 12) is high and is used only when operating on adifferential input voltage. A gain control switch labeled with both an“S” and a “D” is used when operating on either a single ended ordifferential input voltage, depending on the particular control signal(h, m, or l) applied to the switch. A gain control switch having no “S”or “D” label is used when operating on either a single ended ordifferential input voltage.

Moreover, the subset (S318-S328) of the switches is governed by controlsignals h, m, and l as follows. Switch S318 is controlled to close bycontrol signal l when operating on a differential signal. Switch S320 iscontrolled to close by control signal m when operating on a differentialsignal and by control signal l when operating on a single ended signal.Switch S322 is controlled to close by control signal h when operating oneither a single ended or differential signal and by control signal mwhen operating on a single ended signal. Switch S324 is controlled toclose by control signal l when operating on a differential signal.Switch S326 is controlled to close by control signal m when operating ona differential signal and by control signal l when operating on a singleended signal. Switch S328 is controlled to close by control signal hwhen operating on either a single ended or differential signal.

During operation of the initial ADC stage 320, during the same mainclock period in which the comparator and digital circuit 1200 generatesthe initial output bit, the first set of switches (S300-S308) isconfigured to close under the control of the sampling control clocksignal p1 during the sample cycle to charge the capacitors 304 and 306in order to sample an unscaled input voltage at the first voltage input(Vin), thereby generating an unscaled input voltage sample. Upon theconclusion of the sample cycle when control signal p1 controls the firstset of switches to open, the second set of switches (S310-S328) isconfigured to selectively close under the control of the gain controlclock signal p2, the voltage scaling and gain control signal (h, m, orl) generated by the comparator and logic circuit 1200 during the initialmain clock period that initiated the ADC process and the control signal(C_(S) or C_(D)) provided by the finite state machine 1202, to scale theunscaled input voltage sample and generate the initial residue voltagebased on the comparison of the magnitude of the unscaled input voltageto the first upper and lower unscaled voltage trip points (e.g., asshown in diagram 500 or 510 of FIG. 5, depending on whether the unscaledinput voltage comprises a single ended or differential input voltage).

In the illustrative circuit arrangement 320, during the initial residuecalculation phase and when the unscaled input voltage comprises a singleended input voltage, the switched capacitor circuit generates theinitial residue voltage at the node N304 having a magnitude determinedby and in accordance with the sets of equations (1), (2), and (3) above.When the unscaled input voltage comprises a differential input voltage,the switched capacitor circuit generates the initial residue voltage atthe node N304 having a magnitude determined by and in accordance withthe sets of equations (4), (5), and (6) above. The residue voltage isprovided to the next ADC stage 330, which in some embodiments is a 1.5bit RSD ADC stage. In this illustrative pipelined ADC implementation,the ADC stage 330 provides a residue voltage V_(out2) to the next ADCstage (not shown).

As stated earlier, in an alternative embodiment, the ADCs shown in FIG.1 to FIG. 3 can be configured to have a cyclic ADC configuration. Insuch embodiments, a single ADC stage (e.g., ADC stages 120, 220, or 320)is used as the initial stage of the ADC for the initial residuecalculation cycle and then reconfigured to have a circuit arrangementthat does not scale the input voltage, such as 1.5 bit RSD ADC circuitarrangement, for subsequent residue calculation cycles. Thus, in furtheraccordance with the present teachings, after the initial residuecalculation cycle, the second set of (gain control) switches isconfigured to selectively close under the control of the gain controlclock signal and one or more control signals (h, m, l, C_(R)) togenerate a next residue voltage based on a comparison of a magnitude ofthe input voltage (i.e., the initial residue voltage or a residuevoltage from a preceding ADC stage) to the upper and lower residuevoltage trip points (e.g., as shown in diagram 520 of FIG. 5).

Any of circuits 120-320 can be modified to enable this configurationfrom an initial ADC stage to a 1.5 bit RSD ADC circuit arrangement; FIG.4 illustrates such a modification to circuit 320. More particularly,FIG. 4 illustrates is a circuit diagram of a cyclic ADC 400 having, inone embodiment: a first ADC stage 420, a second ADC stage 430, and amultiplexer (“mux”) 440. The ADC stage 420 operates on an unscaledanalog input voltage (Vin) that comprises either a single ended inputvoltage or a differential input voltage, during an initial residuecalculation cycle and operates on a residue voltage (Vout) in subsequentresidue calculation cycles. In the two-stage cyclic ADC embodiment, Vinis received into a first input of the multiplexer 440. An output of theADC stage 430 (labeled as V_(out2)) is coupled to a second input of themultiplexer 440, and an output of the multiplexer 440 is coupled to aninput of the ADC stage 420. The multiplexer 440 contains circuitry (suchas one or more switches) to control whether the unscaled input voltageVin or a residue voltage V_(out2) from the ADC stage 430 is provided tothe ADC stage 420. In an alternate single-stage cyclic ADC embodiment,an output of the ADC stage 420 (labeled as V_(ain)) is coupled to thesecond input of the multiplexer 440 for feeding the initial residuevoltage and subsequent residue voltages generated by the ADC stage 420back to the input of the ADC stage 420.

ADC stage 420 includes a comparator and logic circuit having theconfiguration 1200 illustrated in FIG. 12 and a switched capacitorcircuit 422 coupled to the comparator and logic circuit at a firstvoltage input (labeled as Vin/Vout) of the switched capacitor circuit.The switched capacitor circuit 422 further includes: a second voltageinput (labeled as vref) for receiving a reference voltage; a thirdvoltage input (labeled as −vref) for receiving a negative referencevoltage, a voltage supply node N400 which is coupled to a common modevoltage V_(CM), which in some implementations is a voltage that isapproximately in the middle of the operating range of the ADC stage 420;a voltage output (which is an output V_(out1) of the ADC stage 420) at anode N404; a plurality of coupled switches and capacitors, with theconnectivity of these elements described below; and an operationalamplifier 402 having an inverting input coupled to (“at”) the node N400,a non-inverting input at a node N402, and an output terminal coupled to(and serving as) the voltage output (V_(out1)) of the switched capacitorcircuit, at the node N404. The plurality of coupled capacitors comprisesfour capacitors 404, 406, 408, and 410 each having a same capacitancevalue and each having first and second terminals. As shown, all fourcapacitors have a first terminal coupled together at a node N406. Thesecond terminal of the capacitor 404 is coupled to a node N408. Thesecond terminal of the capacitor 406 is coupled to a node N410. Thesecond terminal of the capacitor 408 is coupled to a node N412. Thesecond terminal of the capacitor 410 is coupled to a node N414.

The plurality of coupled switches comprises a first set of switches(S400, S402, S404, S406, and S408) coupled to the first voltage input(Vin/Vout), the voltage supply node N400 and the four capacitors404-410. The remainder of the plurality of coupled switches comprises asecond set of switches (S410, S412, S414, S416, S418, S420, S422, S424,S426, S428, and S430) that includes a subset of the switches (S414,S416, S418, S420, S422, S424, S426, S328, and S430) that are selectivelycontrolled by control signal (h, m, l) provided by the comparator andlogic circuit 1200 and control signal (C_(S), C_(D), C_(R)) provided bythe finite state machine 1202. The second set of switches (S410-S430) iscoupled to the second voltage input (vref), the third voltage input(−vref), the voltage supply node N400, the four capacitors 404-410, andthe non-inverting input at node N402 and the output (at V_(out1)) of theoperational amplifier 402. Each switch has at least first and secondterminals and can be implemented using any suitable transistortechnology including, but not limited to, MOSFET technology.

The connectivity of the switches within this illustrative switchedcapacitor circuit is as follows. The first terminal of switch S400 iscoupled to the first voltage input (Vin/Vout), and the second terminalis coupled to the node N408. The first terminal of switch S402 iscoupled to the first voltage input (Vin/Vout), and the second terminalis coupled to the node N410. The first terminal of switch S404 iscoupled to the voltage supply node, and the second terminal is coupledto the node N412. The first terminal of switch S406 is coupled to thevoltage supply node, and the second terminal is coupled to the nodeN414. The first terminal of switch S408 is coupled to the voltage supplynode, and the second terminal is coupled to the node N406. The firstterminal of switch S410 is coupled to the node N408, and the secondterminal is coupled to the output of the operational amplifier 402 atthe node N404. The first terminal of switch S412 is coupled to the nodeN406, and the second terminal is coupled to the non-inverting input ofthe operational amplifier 402 at the node N402. The first terminal ofswitch S414 is coupled to the output (V_(out1)), and the second terminalis coupled to the node N410. The first terminal of switch S416 iscoupled to the voltage supply node, and the second terminal is coupledto the node N410. The first terminal of switch S418 is coupled to thesecond voltage input (vref), and the second terminal is coupled to thenode N410. The first terminal of switch S420 is coupled to the thirdvoltage input (−vref), and the second terminal is coupled to the nodeN412. The first terminal of switch S422 is coupled to the voltage supplynode, and the second terminal is coupled to the node N412. The firstterminal of switch S424 is coupled to the second voltage input (vref),and the second terminal is coupled to the node N412. The first terminalof switch S426 is coupled to the third voltage input (−vref), and thesecond terminal is coupled to the node N414. The first terminal ofswitch S428 is coupled to the voltage supply node, and the secondterminal is coupled to the node N414. The first terminal of switch S430is coupled to the second voltage input (vref), and the second terminalis coupled to the node N414.

Each of the plurality of coupled switches is further labeled by theirrespective governing clock signal (p1 or p2) or control signal (h, m, orl) that controls the opening and closing of the switch. Duringoperation, when a clock or control signal is “high”, the associatedswitch is closed; and when a clock or control signal is “low”, theassociated switch is open. More specifically, the first set of switchesS400-S408 (also referred to herein as sampling control switches) isgoverned by a sampling control clock signal p1. The second set ofswitches S410-S430 (also referred to herein as gain control switches) isgoverned by a gain control clock signal p2. In addition, the gaincontrol switches may be labeled with an “S”, a “D”, or an “R”. Moreparticularly, a gain control switch labeled with only an “S” iscontrolled to close only when the control signal C_(S) (FIG. 12) is highand is used only when operating on a single ended input voltage. A gaincontrol switch labeled with only a “D” is controlled to close only whenthe control signal C_(D) (FIG. 12) is high and is used only whenoperating on a differential input voltage. A gain control switch labeledwith only an “R” is controlled to close only when the control signalC_(R) (FIG. 12) is high and is used only when operating on a residueinput voltage. A gain control switch labeled with a combination of an“5”, “D” and/or “R” is used when operating either on a single ended, adifferential or a residue input voltage, depending on the particularcontrol (h, m, or l) signal applied to the switch. A gain control switchhaving no “5”, “D” or “R” is used during all residue calculation cycles.

Moreover, the subset (S420-S430) of the switches is governed by controlsignals h, m, and l as follows. Switch S420 is controlled to close bycontrol signal l when operating on a differential or residue signal.Switch S422 is controlled to close by control signal m when operatingany one of a single ended, differential or residue signal and by controlsignal l when operating on a single ended signal. Switch S424 iscontrolled to close by control signal h when operating on any one of asingle ended, differential or residue signal. Switch S426 is controlledto close by control signal l when operating on a differential signal.Switch S428 is controlled to close by control signal m when operating ona differential signal and by control signal l when operating on a singleended signal. Switch S430 is controlled to close by control signal mwhen operating on a single ended signal and by a control signal h whenoperating on either a single ended or differential signal.

During operation as an initial ADC stage, circuit 420 functions as doesthe circuit 320 of FIG. 3, as described above and not repeated here forthe sake of brevity. During operation as the 1.5 bit RSD ADC stage, thefirst set of switches (S400-S408) is configured to close under thecontrol of the sampling control clock signal p1 during the sample cycleto charge the capacitors 404 and 406 in order to sample a residue inputvoltage at the first voltage input (Vin/Vout), thereby generating aresidue input voltage sample. The residue input voltage comprises theinitial residue voltage or a subsequent residue voltage generated by ADCstage 420 when V_(out1) is coupled to the multiplexer 440 or comprisesthe residue voltage V_(out2) generated by the second ADC stage 430, inthe two-stage ADC embodiment. Upon the conclusion of the sample cyclewhen control signal p1 controls the first set of switches to open, thesecond set of switches (S410-S430) is configured to selectively closeunder the control of the gain control clock signal p2 and one or morecontrol signals (h, m, l, C_(R)) to generate an output residue voltagebased on the comparison of the magnitude of the residue input voltage tothe first upper and lower residue voltage trip points (e.g., as shown indiagram 520 of FIG. 5). The magnitude of the output residue voltage isdetermined in accordance with the following equations: when Vin>Vh,Vout=2Vin−vref; when Vh>Vin>Vl, Vout=2Vin; and when Vin<Vl,Vout=2Vin+vref, wherein Vin is the magnitude of the residue inputvoltage, Vout is the magnitude of the output residue voltage, vref is amagnitude of the reference voltage, Vh is the upper residue voltage trippoint, and Vl is the lower residue voltage trip point.

FIG. 6 to FIG. 10 illustrate embodiments of the present teachings thatintegrate input voltage scaling, reference voltage scaling and aninitial residue voltage calculation within the same operation, i.e., theinitial residue calculation cycle. As mentioned earlier, some of theseembodiments are more suitable to implementation in cyclic ADCs.Therefore, the circuit arrangements 600-900 illustrated, respectively,in FIGS. 6-9 comprise cyclic ADCs, which in one embodiment comprisessingle-stage cyclic ADCs and in an alternative embodiment comprisestwo-stage ADCs. More particularly, a single ADC stage (e.g., ADC stages620, 720, 820, and 920) is used as the initial stage of the ADC for theinitial residue calculation cycle and then reconfigured to have acircuit arrangement that does not scale the input and referencevoltages, such as 1.5 bit RSD ADC circuit arrangement, described above,for subsequent residue calculation cycles. To enable the ADC stages 620,720, 820, and 920, each of these stages comprises a comparator and logiccircuit, configured with multiple upper and lower trip point sets, whichoperates similar to the comparator and logic circuit 1200 of FIG. 12,the description of which is not repeated here for the sake of brevity.

Turning momentarily to FIG. 10, shown therein are diagrams 1000, 1010,and 1020 depicting three example voltage trip point configurations forthe comparator and logic circuit 1200 when the initial ADC stageperforms unscaled input voltage scaling, reference voltage scaling, andinitial residue calculation during the initial residue calculationcycle, as described for instance by reference to FIG. 6 to FIG. 9. Inaccordance with the present teachings, ADC embodiments have thecapability of handling both single ended input voltages and differentialinput voltages. Thus, in an embodiment (e.g., ADC implementations shownin FIGS. 6, 8, and 9, the comparator and logic circuit 1200 isconfigured with first upper and lower unscaled voltage trip points, forinstance the voltage trip points having values (V_(H)=⅝vref andV_(L)=⅜vref from a range of 0 to vref) shown in diagram 1000, to processa single ended input voltage prior to the initial residue calculationcycle. Vref is a reference voltage provided to the switched capacitorcircuit of the ADC stages. The comparator and logic circuit 1200 isfurther configured (e.g., for ADC implementations shown in FIGS. 7-9)with second upper and lower unscaled voltage trip points that aredifferent than the first upper and lower unscaled voltage trip points,for instance the voltage trip points having values (V_(H)=¼vref andV_(L)=−¼vref from a range of −vref to vref) shown in diagram 1010, toprocess a differential input voltage prior to the initial residuecalculation cycle. Moreover, the comparator and logic circuit 1200 isconfigured (e.g., for ADC implementations shown in FIGS. 6-9) with upperand lower residue voltage trip points that are different than the firstand second upper and lower unscaled voltage trip points, for instancethe voltage trip points having values (V_(H)=⅛vref and V_(L)=−⅛vref froma range of −vref/2 to vref/2) shown in diagram 1020, to process residuevoltages after the initial residue calculation cycle and for eachremaining residue calculation cycle of the ADC process.

Turning now to FIG. 6, shown therein is a circuit diagram illustrating acyclic ADC 600 having an initial ADC stage 620 performing input andreference voltage scaling and an initial residue voltage calculation inthe same operation, in accordance with another embodiment. The ADC stage620 operates on an unscaled analog input voltage (Vin) that comprises asingle ended input voltage, during the initial residue calculationcycle. Thereafter, during subsequent residue calculation cycles, the ADCstage 620 is reconfigured using the control signal C_(R) (FIG. 12) toreceive a residue voltage at its input (labeled Vin/Vout) and togenerate a next residue voltage at its output (labeled V_(out1)),without scaling the input voltage. The ADC stage 620 maintains thisconfiguration until the next unscaled input voltage sample is taken,wherein the ADC stage 620 is reconfigured using the control signal C_(S)(FIG. 12) to generate another initial residue voltage. The ADC 600further includes a multiplexer 640 having a first input coupled toreceive the analog input voltage Vin, a second input coupled to receivea residue voltage and an output coupled to the input of the ADC stage620. The multiplexer 640 contains circuitry (such as one or moreswitches) to control whether the unscaled input voltage or a residuevoltage is provided at the input of the ADC stage 620. In a single-stagecyclic ADC 600 embodiment, initial and subsequent residue voltages(V_(out1)) output by the ADC stage 620 are coupled to the second inputof the multiplexer 640. In a two-stage cyclic ADC embodiment, the ADC600 comprises a second ADC stage 630 that provides residue voltagesV_(out2) to the second input of the multiplexer 640. The ADC stage 630,in one embodiment, operates as a known 1.5 bit RSD ADC.

ADC stage 620 includes a comparator and logic circuit (not shown) thatcan be configured, as the comparator and logic circuit 1200 of FIG. 12,with upper and lower unscaled voltage trip points V_(HS) and V_(LS)(having values, for instance, as shown in diagram 1000 of FIG. 10) priorto the initial residue calculation and configured with upper and lowerresidue voltage trip points V_(HR) and V_(LR) (having values, forinstance, as shown in diagram 1020 of FIG. 10) for enabling thecalculation of residue voltages. The ADC stage 620 further comprises aswitched capacitor circuit 622 coupled to the comparator and logiccircuit at a first voltage input (labeled as Vin/Vout) of the switchedcapacitor circuit. For ease of description only the circuit schematic ofthe switched capacitor circuit 622 when the ADC stage 620 functions asthe initial ADC stage is shown and described. An example of additionalcircuitry to enable the ADC stage to be reconfigured from an initialstage to generate residue voltages for subsequent residue calculationcycles is shown by reference to FIG. 9.

The switched capacitor circuit 622 further includes: a second voltageinput (labeled as vref) for receiving a reference voltage; a voltagesupply node N600 which is coupled to a common mode voltage V_(CM), whichin some implementations is a voltage that is approximately in the middleof the operating range of the ADC stage 620; a voltage output (which isan output V_(out1) of the ADC stage 620 at a node N604); a plurality ofcoupled switches and capacitors, with the connectivity of these elementsdescribed below; and an operational amplifier 602 having an invertinginput coupled to (“at”) the node N600, a non-inverting input at a nodeN602, and an output terminal coupled to (and serving as) the voltageoutput (V_(out1)) of the switched capacitor circuit, at the node N604.The plurality of coupled capacitors comprises four capacitors 604, 606,608, and 610, with three of the capacitors (606, 608, and 610) having asame first capacitance value and the fourth capacitor 604 having twicethe first capacitance value; and with each capacitor 604-610 havingfirst and second terminals. As shown, all four capacitors have a firstterminal coupled together at a node N606. The second terminal of thecapacitor 604 is coupled to a node N608. The second terminal of thecapacitor 606 is coupled to a node N610. The second terminal of thecapacitor 608 is coupled to a node N612. The second terminal of thecapacitor 610 is coupled to a node N614.

The plurality of coupled switches comprises a first set of switches(S600, S602, S604, S606, and S608) coupled to the first voltage input(Vin/Vout), the voltage supply node N600 and the four capacitors604-610. The remainder of the plurality of coupled switches comprises asecond set of switches (S610, S612, S614, S616, S618, S620, and S622)that includes a subset of the switches (S616, S618, S620, and S622) thatare selectively controlled by the voltage scaling and gain controlsignal (h, m, l) provided by the comparator and logic circuit 112. Thesecond set of switches (S610-S622) is coupled to the second voltageinput (vref), the voltage supply node N600, the four capacitors 604-610,and the non-inverting input at node N602 and the output (at V_(out1)) ofthe operational amplifier 602. Each switch has at least first and secondterminals and can be implemented using any suitable transistortechnology including, but not limited to, MOSFET technology.

The connectivity of the switches within this illustrative switchedcapacitor circuit is as follows. The first terminal of switch S600 iscoupled to the first voltage input (Vin/Vout), and the second terminalis coupled to the node N608. The first terminal of switch S602 iscoupled to the first voltage input (Vin/Vout), and the second terminalis coupled to the node N610. The first terminal of switch S604 iscoupled to the first voltage input (Vin/Vout), and the second terminalis coupled to the node N612. The first terminal of switch S606 iscoupled to the voltage supply node, and the second terminal is coupledto the node N614. The first terminal of switch S608 is coupled to thevoltage supply node, and the second terminal is coupled to the nodeN606. The first terminal of switch S610 is coupled to the node N608, andthe second terminal is coupled to the output of the operationalamplifier 602 at the node N604. The first terminal of switch S612 iscoupled to the node N606, and the second terminal is coupled to thenon-inverting input of the operational amplifier 602 at the node N602.The first terminal of switch S614 is coupled to the second voltage input(vref), and the second terminal is coupled to the node N610. The firstterminal of switch S616 is coupled to the voltage supply node, and thesecond terminal is coupled to the node N612. The first terminal ofswitch S618 is coupled to the second voltage input (vref), and thesecond terminal is coupled to the node N612. The first terminal ofswitch S620 is coupled to the voltage supply node, and the secondterminal is coupled to the node N614. The first terminal of switch S622is coupled to the second voltage input (vref), and the second terminalis coupled to the node N614.

Each of the plurality of coupled switches is further labeled by theirrespective governing clock signal (p1 or p2) or control signal (h, m, orl) that controls the opening and closing of the switch. Duringoperation, when a clock or control signal is “high”, the associatedswitch is closed; and when a clock or control signal is “low”, theassociated switch is open. More specifically, the first set of switchesS600-S608 (also referred to herein as sampling control switches) isgoverned by a sampling control clock signal p1. The second set ofswitches S610-S622 (also referred to herein as gain control switches) isgoverned by a gain control clock signal p2. The subset (S616-S622) ofthe switches is governed by control signals h, m, and l with: switchS616 being controlled to close by control signal l; switch S618 beingcontrolled to close by control signals h or m; switch S620 beingcontrolled to close by control signal l; and switch S622 beingcontrolled to close by control signal h.

During operation of the initial ADC stage 620, during the same mainclock period in which the comparator and digital circuit 1200 generatesthe initial output bit, the first set of switches (S600-S608) isconfigured to close under the control of the sampling control clocksignal p1 during the sample cycle to charge the capacitors 604-608 inorder to sample an unscaled input voltage at the first voltage input(Vin/Vout), thereby generating an unscaled input voltage sample. Uponthe conclusion of the sample cycle when control signal p1 controls thefirst set of switches to open, the second set of switches (S610-S622) isconfigured to selectively close under the control of the gain controlclock signal p2 and the voltage scaling and gain control signal (h, m,or l), generated by the comparator and logic circuit 1200 during theinitial main clock period that initiated the ADC process, to scale theunscaled input voltage sample and the reference voltage and generate theinitial residue voltage based on the comparison of the magnitude of theunscaled input voltage to the first upper and lower unscaled voltagetrip points (e.g., as shown in diagram 1000 of FIG. 10).

In the illustrative circuit arrangement 620, during the initial residuecalculation phase and when the unscaled input voltage comprises a singleended input voltage, the switched capacitor circuit generates theinitial residue voltage at the node N104 having a magnitude determinedby and in accordance with the following sets of equations:

$\begin{matrix}\begin{matrix}\begin{matrix}\underset{\_}{{when},{{Vin} > {Vh}}} \\{{{Vout} = {{2\left( {{Vin} - \frac{vref}{2}} \right)} - \frac{vref}{2}}};}\end{matrix} \\{{2{Vout}} = {{4{Vin}} - {3{vref}}}}\end{matrix} & (7) \\\begin{matrix}\begin{matrix}\underset{\_}{{when},{{Vh} > {Vin} > {V\; 1}}} \\{{{Vout} = {2\left( {{Vin} - \frac{vref}{2}} \right)}};}\end{matrix} \\{{Vout} = {{4{Vin}} - {20{vref}}}}\end{matrix} & (8) \\\begin{matrix}\begin{matrix}\underset{\_}{{when},{{Vin} < {V\; 1}}} \\{{{Vout} = {{2\left( {{Vin} - \frac{vref}{2}} \right)} + \frac{vref}{2}}},}\end{matrix} \\{{2{Vout}} = {{4{Vin}} - {vref}}}\end{matrix} & (9)\end{matrix}$wherein Vin is the magnitude of the unscaled input voltage, Vout is theinitial residue magnitude, vref is a magnitude of the reference voltage,Vh is the upper unscaled voltage trip point, and Vl is the lowerunscaled voltage trip point. In the sets of equations (7), (8), and (9),the magnitude (Vin) of the unscaled input voltage is scaled by (−2vref)and the reference voltage is scaled by (½) to maintain the input andreference voltages within operating range of the operational amplifier102. The residue voltage is provided to the next ADC stage 630 or themultiplexer 640, depending on the embodiment.

Turning now to FIG. 7, shown therein is a circuit diagram illustrating acyclic ADC 700 comprising an initial ADC stage 720 performing input andreference voltage scaling and an initial residue voltage calculation inthe same operation, in accordance with another embodiment. The ADC stage720 operates on an unscaled analog input voltage that comprises adifferential input voltage, during the initial residue calculationcycle. Thereafter, during subsequent residue calculation cycles, the ADCstage 720 is reconfigured using the control signal C_(R) (FIG. 12) toreceive a residue voltage at its input (labeled Vin/Vout) and togenerate a next residue voltage at its output (labeled V_(out1)),without scaling the input voltage. The ADC stage 720 maintains thisconfiguration until the next unscaled input voltage sample is taken,wherein the ADC stage 720 is reconfigured using the control signal C_(D)(FIG. 12) to generate another initial residue voltage. The ADC 700further includes a multiplexer 740 having a first input coupled toreceive the analog input voltage Vin, a second input coupled to receivea residue voltage and an output coupled to the input of the ADC stage720. The multiplexer 740 contains circuitry (such as one or moreswitches) to control whether the unscaled input voltage or a residuevoltage is provided at the input of the ADC stage 720. In a single-stagecyclic ADC 700 embodiment, initial and subsequent residue voltages(V_(out1)) output by the ADC stage 720 are coupled to the second inputof the multiplexer 740. In a two-stage cyclic ADC embodiment, the ADC700 comprises a second ADC stage 730 that provides residue voltagesV_(out2) to the second input of the multiplexer 740. The ADC stage 730,in one embodiment, operates as a known 1.5 bit RSD ADC.

ADC stage 720 includes a comparator and logic circuit (not shown) thatcan be configured, as the comparator and logic circuit 1200 of FIG. 12,with upper and lower unscaled voltage trip points V_(HD) and V_(LD)(having values, for instance, as shown in diagram 1010 of FIG. 10) priorto the initial residue calculation and configured with upper and lowerresidue voltage trip points V_(HR) and V_(LR) (having values, forinstance, as shown in diagram 1020 of FIG. 10) for enabling thecalculation of residue voltages. The ADC stage 720 further comprises aswitched capacitor circuit 722 coupled to the comparator and logiccircuit at a first voltage input (labeled as Vin/Vout) of the switchedcapacitor circuit. For ease of description only the circuit schematic ofthe switched capacitor circuit 722 when the ADC stage 720 functions asthe initial ADC stage is shown and described. An example of additionalcircuitry to enable an ADC stage to be reconfigured from an initialstage to generate residue voltages for subsequent residue calculationcycles is shown by reference to FIG. 9.

The switched capacitor circuit 722 further includes: a second voltageinput (labeled as vref) for receiving a reference voltage; a thirdvoltage input (labeled as −vref) for receiving a negative referencevoltage, a voltage supply node N700 which is coupled to a common modevoltage V_(CM), which in some implementations is a voltage that isapproximately in the middle of the operating range of the ADC stage720); a voltage output (which is an output V_(out1) of the ADC stage720) at a node N704; a plurality of coupled switches and capacitors,with the connectivity of these elements described below; and anoperational amplifier 702 having an inverting input coupled to (“at”)the node N700, a non-inverting input at a node N702, and an outputterminal coupled to (and serving as) the voltage output (V_(out1)) ofthe switched capacitor circuit, at the node N704. The plurality ofcoupled capacitors comprises five capacitors 704, 706, 708, 710, and712, with four of the capacitors (706, 708, 710, and 712) having a samefirst capacitance value and the fifth capacitor 704 having twice thefirst capacitance value; and with each capacitor having first and secondterminals. As shown, all five capacitors have a first terminal coupledtogether at a node N706. The second terminal of the capacitor 704 iscoupled to a node N708. The second terminal of the capacitor 706 iscoupled to a node N710. The second terminal of the capacitor 708 iscoupled to a node N712. The second terminal of the capacitor 710 iscoupled to a node N714. The second terminal of the capacitor 712 iscoupled to a node N716.

The plurality of coupled switches comprises a first set of switches(S700, S702, S704, S706, S708, and S710) coupled to the first voltageinput (Vin/Vout), the voltage supply node N700 and the five capacitors704-712. The remainder of the plurality of coupled switches comprises asecond set of switches (S712, S714, S716, S718, S720, S722, S724, S726,S728, and S730) that includes a subset of the switches (S720, S722,S724, S726, S728, and S730) that are selectively controlled by thevoltage scaling and gain control signal (h, m, l) provided by thecomparator and logic circuit 1200. The second set of switches(S712-S730) is coupled to the second voltage input (vref), the thirdvoltage input (−vref), the voltage supply node N700, the five capacitors704-712, and the non-inverting input at node N702 and the output (atV_(out1)) of the operational amplifier 702. Each switch has at leastfirst and second terminals and can be implemented using any suitabletransistor technology including, but not limited to, MOSFET technology.

The connectivity of the switches within this illustrative switchedcapacitor circuit is as follows. The first terminal of switch S700 iscoupled to the first voltage input (Vin/Vout), and the second terminalis coupled to the node N708. The first terminal of switch S702 iscoupled to the first voltage input (Vin), and the second terminal iscoupled to the node N710. The first terminal of switch S704 is coupledto the first voltage input (Vin/Vout), and the second terminal iscoupled to the node N712. The first terminal of switch S706 is coupledto the voltage supply node, and the second terminal is coupled to thenode N714. The first terminal of switch S708 is coupled to the voltagesupply node, and the second terminal is coupled to the node N716. Thefirst terminal of switch S710 is coupled to the voltage supply node, andthe second terminal is coupled to the node N706. The first terminal ofswitch S712 is coupled to the node N708, and the second terminal iscoupled to the output of the operational amplifier 702 at the node N704.The first terminal of switch S714 is coupled to the node N706, and thesecond terminal is coupled to the non-inverting input of the operationalamplifier 702 at the node N702. The first terminal of switch S716 iscoupled to the output (V_(out1)), and the second terminal is coupled tothe node N710. The first terminal of switch S718 is coupled to theoutput (V_(out1)), and the second terminal is coupled to the node N712.The first terminal of switch S720 is coupled to the third voltage input(−vref), and the second terminal is coupled to the node N714. The firstterminal of switch S722 is coupled to the voltage supply node, and thesecond terminal is coupled to the node N714. The first terminal ofswitch S724 is coupled to the second voltage input (vref), and thesecond terminal is coupled to the node N714. The first terminal ofswitch S726 is coupled to the third voltage input (−vref), and thesecond terminal is coupled to the node N716. The first terminal ofswitch S728 is coupled to the voltage supply node, and the secondterminal is coupled to the node N716. The first terminal of switch S730is coupled to the second voltage input (vref), and the second terminalis coupled to the node N716.

Each of the plurality of coupled switches is further labeled by theirrespective governing clock signal (p1 or p2) or control signal (h, m, orl) that controls the opening and closing of the switch. Duringoperation, when a clock or control signal is “high”, the associatedswitch is closed; and when a clock or control signal is “low”, theassociated switch is open. More specifically, the first set of switchesS700-S710 (also referred to herein as sampling control switches) isgoverned by a sampling control clock signal p1. The second set ofswitches S712-S730 (also referred to herein as gain control switches) isgoverned by a gain control clock signal p2. The subset (S720-S730) ofthe switches is governed by control signals h, m, and l with: switchS720 being controlled to close by control signal l; switch S722 beingcontrolled to close by control signal m; switch S724 being controlled toclose by control signal h; and switch S726 being controlled to close bycontrol signal l; switch S728 being controlled to close by controlsignal m; and switch S730 being controlled to close by control signal h.

During operation of the initial ADC stage 720, during the same mainclock period in which the comparator and digital circuit 1200 generatesthe initial output bit, the first set of switches (S700-S710) isconfigured to close under the control of the sampling control clocksignal p1 during the sample cycle to charge the capacitors 704-708 inorder to sample an unscaled input voltage at the first voltage input(Vin), thereby generating an unscaled input voltage sample. Upon theconclusion of the sample cycle when control signal p1 controls the firstset of switches to open, the second set of switches (S712-S730) isconfigured to selectively close under the control of the gain controlclock signal p2 and the voltage scaling and gain control signal (h, m,or l), generated by the comparator and logic circuit 1200 during theinitial main clock period that initiated the ADC process, to scale theunscaled input voltage sample and the reference voltage and generate theinitial residue voltage based on the comparison of the magnitude of theunscaled input voltage to the first upper and lower unscaled voltagetrip points (e.g., as shown in diagram 1010 of FIG. 10).

In the illustrative circuit arrangement 720, during the initial residuecalculation cycle and when the unscaled input voltage comprises adifferential input voltage, the switched capacitor circuit generates theinitial residue voltage at the node N704 having a magnitude determinedby and in accordance with the following sets of equations:

$\begin{matrix}\begin{matrix}\begin{matrix}\underset{\_}{{when},{{Vin} > {Vh}}} \\{{{Vout} = {{2\left( \frac{Vin}{2} \right)} - \frac{vref}{2}}};}\end{matrix} \\{{4{Vout}} = {{4{Vin}} - {2{vref}}}}\end{matrix} & (10) \\\begin{matrix}\begin{matrix}\underset{\_}{{when},{{Vh} > {Vin} > {V\; 1}}} \\{{{Vout} = {2\left( \frac{Vin}{2} \right)}};}\end{matrix} \\{{4{Vout}} = {4{Vin}}}\end{matrix} & (11) \\\begin{matrix}\begin{matrix}\underset{\_}{{when},{{Vin} < {V\; 1}}} \\{{{Vout} = {{2\left( \frac{Vin}{2} \right)} + \frac{vref}{2}}},}\end{matrix} \\{{4{Vout}} = {{4{Vin}} + {2{vref}}}}\end{matrix} & (12)\end{matrix}$wherein Vin is the magnitude of the unscaled input voltage, Vout is theinitial residue magnitude, vref is a magnitude of the reference voltage,Vh is the upper unscaled voltage trip point, and Vl is the lowerunscaled voltage trip point. In the sets of equations (10), (11), and(12), the magnitude (Vin) of the unscaled input voltage is scaled by (½)and the reference voltage is scaled by (½) to maintain the input andreference voltages within operating range of the operational amplifier702. The residue voltage is provided to the next ADC stage 730 or to themultiplexer 740, depending on the embodiment.

Turning now to FIG. 8, shown therein is a circuit diagram illustratingan initial ADC stage 820 performing input and reference voltage scalingand an initial residue voltage calculation in the same operation, inaccordance with another embodiment. The ADC stage 820 operates on anunscaled analog input voltage that comprises either a single ended inputvoltage or a differential input voltage, during the initial residuecalculation cycle. Thereafter, during subsequent residue calculationcycles, the ADC stage 820 is reconfigured using the control signal C_(R)(FIG. 12) to receive a residue voltage at its input (labeled Vin/Vout)and to generate a next residue voltage at its output (labeled V_(out1)),without scaling the input voltage. The ADC stage 820 maintains thisconfiguration until the next unscaled input voltage sample is taken,wherein the ADC stage 820 is reconfigured using the control signal C_(S)or C_(D) (FIG. 12), depending on whether the unscaled input signal wassingle ended or differential, to generate another initial residuevoltage. The ADC 800 further includes a multiplexer 840 having a firstinput coupled to receive the analog input voltage Vin, a second inputcoupled to receive a residue voltage and an output coupled to the inputof the ADC stage 820. The multiplexer 840 contains circuitry (such asone or more switches) to control whether the unscaled input voltage or aresidue voltage is provided at the input of the ADC stage 820. In asingle-stage cyclic ADC 800 embodiment, initial and subsequent residuevoltages (V_(out1)) output by the ADC stage 820 are coupled to thesecond input of the multiplexer 840. In a two-stage cyclic ADCembodiment, the ADC 800 comprises a second ADC stage 830 that providesresidue voltages V_(out2) to the second input of the multiplexer 840.The ADC stage 830, in one embodiment, operates as a known 1.5 bit RSDADC.

ADC stage 820 includes a comparator and logic circuit (not shown) thatcan be configured, as the comparator and logic circuit 1200 of FIG. 12,with upper and lower unscaled voltage trip points V_(HS) and V_(LS) orV_(HD) and V_(LD) (having values, for instance, as shown in diagram 1000or 1010 of FIG. 10) prior to the initial residue calculation andconfigured with upper and lower residue voltage trip points V_(HR) andV_(LR) (having values, for instance, as shown in diagram 1020 of FIG.10) for enabling the calculation of residue voltages. The ADC stage 820further comprises a switched capacitor circuit 822 coupled to thecomparator and logic circuit at a first voltage input (labeled asVin/Vout) of the switched capacitor circuit. For ease of descriptiononly the circuit schematic of the switched capacitor circuit 822 whenthe ADC stage 820 functions as the initial ADC stage is shown anddescribed. An example of additional circuitry to enable the ADC stage tobe reconfigured from an initial stage to generate residue voltages forsubsequent residue calculation cycles is shown by reference to FIG. 9.

The switched capacitor circuit 822 further includes: a second voltageinput (labeled as vref) for receiving a reference voltage; a thirdvoltage input (labeled as −vref) for receiving a negative referencevoltage, a voltage supply node N800 which is coupled to a common modevoltage V_(CM), which in some implementations is a voltage that isapproximately in the middle of the operating range of the operationalamplifier 802); a voltage output (which is an output V_(out1) of the ADCstage 820) at a node N804; a plurality of coupled switches andcapacitors, with the connectivity of these elements described below; andan operational amplifier 802 having an inverting input coupled to (“at”)the node N800, a non-inverting input at a node N802, and an outputterminal coupled to (and serving as) the voltage output (V_(out1)) ofthe switched capacitor circuit, at the node N804. The plurality ofcoupled capacitors comprises five capacitors 804, 806, 808, 810, and812, with four of the capacitors having a same first capacitance valueand the fifth capacitor having twice the first capacitance value, andeach having first and second terminals. As shown, all five capacitorshave a first terminal coupled together at a node N806. The secondterminal of the capacitor 804 is coupled to a node N808. The secondterminal of the capacitor 806 is coupled to a node N810. The secondterminal of the capacitor 808 is coupled to a node N812. The secondterminal of the capacitor 810 is coupled to a node N814. The secondterminal of the capacitor 812 is coupled to a node N816.

The plurality of coupled switches comprises a first set of switches(S800, S802, S804, S806, S808, and S810) coupled to the first voltageinput (Vin/Vout), the voltage supply node N800 and the five capacitors804-812. The remainder of the plurality of coupled switches comprises asecond set of switches (S812, S814, S816, S818, S820, S822, S824, S826,S828, S830, S832, S834, S836) that includes a subset of the switches(S816, S818, S820, S822, S824, S826, S828, S830, S832, S834, S836) thatare selectively controlled by the voltage scaling and gain controlsignal (h, m, l) provided by the comparator and logic circuit 1200 andat least the control signals C_(S) and C_(D) provided by the finitestate machine 1202. The second set of switches (S812-S836) is coupled tothe second voltage input (vref), the third voltage input (−vref), thevoltage supply node N800, the five capacitors 804-812, and thenon-inverting input at node N802 and the output (at Vout) of theoperational amplifier 802. Each switch has at least first and secondterminals and can be implemented using any suitable transistortechnology including, but not limited to, MOSFET technology.

The connectivity of the switches within this illustrative switchedcapacitor circuit is as follows. The first terminal of switch S800 iscoupled to the first voltage input (Vin/Vout), and the second terminalis coupled to the node N808. The first terminal of switch S802 iscoupled to the first voltage input (Vin/Vout), and the second terminalis coupled to the node N810. The first terminal of switch S804 iscoupled to the first voltage input (Vin/Vout), and the second terminalis coupled to the node N812. The first terminal of switch S806 iscoupled to the voltage supply node, and the second terminal is coupledto the node N814. The first terminal of switch S808 is coupled to thevoltage supply node, and the second terminal is coupled to the nodeN816. The first terminal of switch S810 is coupled to the voltage supplynode, and the second terminal is coupled to the node N806. The firstterminal of switch S812 is coupled to the node N808, and the secondterminal is coupled to the output of the operational amplifier 802 atthe node N804. The first terminal of switch S814 is coupled to the nodeN806, and the second terminal is coupled to the non-inverting input ofthe operational amplifier 802 at the node N802. The first terminal ofswitch S816 is coupled to the output (V_(out1)), and the second terminalis coupled to the node N810. The first terminal of switch S820 iscoupled to the second voltage input (vref), and the second terminal iscoupled to the node N810. The first terminal of switch S818 is coupledto the output (V_(out1)), and the second terminal is coupled to the nodeN812. The first terminal of switch S822 is coupled to the voltage supplynode, and the second terminal is coupled to the node N812. The firstterminal of switch S824 is coupled to the second voltage input (vref),and the second terminal is coupled to the node N812. The first terminalof switch S826 is coupled to the third voltage input (−vref), and thesecond terminal is coupled to the node N814. The first terminal ofswitch S828 is coupled to the voltage supply node, and the secondterminal is coupled to the node N814. The first terminal of switch S830is coupled to the second voltage input (vref), and the second terminalis coupled to the node N814. The first terminal of switch S832 iscoupled to the third voltage input (−vref), and the second terminal iscoupled to the node N816. The first terminal of switch S834 is coupledto the voltage supply node, and the second terminal is coupled to thenode N816. The first terminal of switch S836 is coupled to the secondvoltage input (vref), and the second terminal is coupled to the nodeN816.

Each of the plurality of coupled switches is further labeled by theirrespective governing clock signal (p1 or p2) or control signal (h, m, orl) that controls the opening and closing of the switch. Duringoperation, when a clock or control signal is “high”, the associatedswitch is closed; and when a clock or control signal is “low”, theassociated switch is open. More specifically, the first set of switchesS800-S810 (also referred to herein as sampling control switches) isgoverned by a sampling control clock signal p1. The second set ofswitches S812-S836 (also referred to herein as gain control switches) isgoverned by a gain control clock signal p2. In addition, the gaincontrol switches may be labeled with an “S” or “D”. More particularly, again control switch labeled with only an “S” is controlled to close onlywhen the control signal C_(S) (FIG. 12) is high and is used only whenoperating on a single ended input voltage. A gain control switch labeledwith only a “D” is controlled to close only when the controls signalC_(D) (FIG. 12) is high and is used only when operating on adifferential input voltage. A gain control switch labeled with both an“S” and a “D” is used when operating on either a single ended ordifferential input voltage, depending on the particular control signal(h, m, l) applied to the switch. A gain control switch having no “S” or“D” label is used when operating on either a single ended ordifferential input voltage.

Moreover, the subset (S822-S836) of the switches is governed by controlsignals h, m, and l as follows. Switch S822 is controlled to close bycontrol signal l when operating on a single ended signal. Switch S824 iscontrolled to close by control signals h or m when operating on a singleended signal. Switch S826 is controlled to close by control signal lwhen operating on a differential signal. Switch S828 is controlled toclose by control signal m when operating on a differential signal and bycontrol signal l when operating on a single ended signal. Switch S830 iscontrolled to close by control signal h when operating on either asingle ended or differential signal. Switch S832 is controlled to closeby control signal l when operating on a differential signal. Switch S834is controlled to close by control signal m when operating on a singleended signal. Switch S836 is controlled to close by control signal hwhen operating on a differential signal.

During operation of the initial ADC stage 820, during the same mainclock period in which the comparator and digital circuit 1200 generatesthe initial output bit, the first set of switches (S800-S810) isconfigured to close under the control of the sampling control clocksignal p1 during the sample cycle to charge the capacitors 804-808 inorder to sample an unscaled input voltage at the first voltage input(Vin/Vout), thereby generating an unscaled input voltage sample. Uponthe conclusion of the sample cycle when control signal p1 controls thefirst set of switches to open, the second set of switches (S812-S836) isconfigured to selectively close under the control of the gain controlclock signal p2, the voltage scaling and gain control signal (h, m, orl) generated by the comparator and logic circuit 1200 during the initialmain clock period that initiated the ADC process, and the control signal(C_(S) or C_(D)) provided by the finite stage machine 1202, to scale theunscaled input voltage sample and the reference voltage and generate theinitial residue voltage based on the comparison of the magnitude of theunscaled input voltage to the first upper and lower unscaled voltagetrip points (e.g., as shown in diagram 1000 or 1010 of FIG. 10,depending on whether the unscaled input voltage comprises a single endedor differential input voltage).

In the illustrative circuit arrangement 820, during the initial residuecalculation phase and when the unscaled input voltage comprises a singleended input voltage, the switched capacitor circuit generates theinitial residue voltage at the node N804 having a magnitude determinedby and in accordance with the sets of equations (7), (8), and (9) above.When the unscaled input voltage comprises a differential input voltage,the switched capacitor circuit generates the initial residue voltage atthe node N804 having a magnitude determined by and in accordance withthe sets of equations (10), (11), and (12) above. The residue voltage isprovided to the next ADC stage 830 or to the multiplexer 840, dependingon the implementation.

As mentioned earlier, any of circuits 620-820 can be modified to enablea configuration from an initial ADC stage, in accordance to the presentteachings, to a RSD ADC stage that does not perform input voltagescaling; FIG. 9 illustrates such a modification to circuit 820. FIG. 9illustrates a circuit diagram of a cyclic ADC 900 having an initial ADCstage 920 performing input and reference voltage scaling and an initialresidue voltage calculation in the same operation, in accordance withanother embodiment. The ADC 920 operates on an unscaled analog inputvoltage that comprises either a single ended input voltage or adifferential input voltage, during the initial residue calculationcycle. Thereafter, during subsequent residue calculation cycles, the ADCstage 920 is reconfigured using the control signal C_(R) (FIG. 12) toreceive a residue voltage at its input (labeled Vin/Vout) and togenerate a next residue voltage at its output (labeled V_(out1)),without scaling the input voltage. The ADC stage 920 maintains thisconfiguration until the next unscaled input voltage sample is taken,wherein the ADC stage 920 is reconfigured using the control signal C_(S)or C_(D) (FIG. 12), depending on whether the unscaled input signal wassingle ended or differential, to generate another initial residuevoltage. The ADC 900 further includes a multiplexer 940 having a firstinput coupled to receive the analog input voltage Vin, a second inputcoupled to receive a residue voltage and an output coupled to the inputof the ADC stage 920. The multiplexer 940 contains circuitry (such asone or more switches) to control whether the unscaled input voltage or aresidue voltage is provided at the input of the ADC stage 920. In asingle-stage cyclic ADC 900 embodiment, initial and subsequent residuevoltages (V_(out1)) output by the ADC stage 920 are coupled to thesecond input of the multiplexer 940. In a two-stage cyclic ADCembodiment, the ADC 900 comprises a second ADC stage 930 that providesresidue voltages V_(out2) to the second input of the multiplexer 940.The ADC stage 930, in one embodiment, operates as a known 1.5 bit RSDADC.

ADC stage 920 includes a comparator and logic circuit (not shown) thatcan be configured, as the comparator and logic circuit 1200 of FIG. 12,with upper and lower unscaled voltage trip points V_(HS) and V_(LS) orV_(HD) and V_(LD) (having values, for instance, as shown in diagram 1000or 1010 of FIG. 10) prior to the initial residue calculation andconfigured with upper and lower residue voltage trip points V_(HR) andV_(LR) (having values, for instance, as shown in diagram 1020 of FIG.10) for enabling the calculation of residue voltages. The ADC stage 920further comprises a switched capacitor circuit 922 coupled to thecomparator and logic circuit at a first voltage input (labeled asVin/Vout) of the switched capacitor circuit.

The switched capacitor circuit 922 further includes: a second voltageinput (labeled as vref) for receiving a reference voltage; a thirdvoltage input (labeled as −vref) for receiving a negative referencevoltage, a voltage supply node N900 which is coupled to a common modevoltage V_(CM), which in some implementations is a voltage that isapproximately in the middle of the operating range of the ADC stage920); a voltage output (which is an output V_(out1) of the ADC stage920) at a node N904; a plurality of coupled switches and capacitors,with the connectivity of these elements described below; and anoperational amplifier 902 having an inverting input coupled to (“at”)the node N900, a non-inverting input at a node N902, and an outputterminal coupled to (and serving as) the voltage output (V_(out1)) ofthe switched capacitor circuit, at the node N904. The plurality ofcoupled capacitors comprises five capacitors 904, 906, 908, 910, and912, with four of the capacitors (906, 908, 910, and 912) having a samefirst capacitance value and the fifth capacitor 904 having twice thefirst capacitance value, and each having first and second terminals. Asshown, all five capacitors have a first terminal coupled together at anode N906. The second terminal of the capacitor 904 is coupled to a nodeN908. The second terminal of the capacitor 906 is coupled to a nodeN910. The second terminal of the capacitor 908 is coupled to a nodeN912. The second terminal of the capacitor 910 is coupled to a nodeN914. The second terminal of the capacitor 912 is coupled to a nodeN916.

The plurality of coupled switches comprises a first set of switches(S900, S902, S904, S906, S908, and S910) coupled to the first voltageinput (Vin/Vout), the voltage supply node N900 and the five capacitors904-912. The remainder of the plurality of coupled switches comprises asecond set of switches (S912, S914, S916, S918, S920, S922, S924, S926,S928, S930, S932, S934, S936, S938, and S940) that includes a subset ofthe switches (S912, S914, S916, S918, S920, S922, S924, S926, S928,S930, S932, S934, and S936) that are selectively controlled by thevoltage scaling and gain control signal (h, m, l) provided by thecomparator and logic circuit 1200 and control signal (C_(S), C_(D),C_(R)) provided by the finite state machine 1202. The second set ofswitches (S912-S940) is coupled to the second voltage input (vref), thethird voltage input (−vref), the voltage supply node S900, the fivecapacitors 904-912, and the non-inverting input at node N902 and theoutput (at V_(out1)) of the operational amplifier 902. Each switch hasat least first and second terminals and can be implemented using anysuitable transistor technology including, but not limited to, MOSFETtechnology.

The connectivity of the switches within this illustrative switchedcapacitor circuit is as follows. The first terminal of switch S900 iscoupled to the first voltage input (Vin/Vout), and the second terminalis coupled to the node N908. The first terminal of switch S902 iscoupled to the first voltage input (Vin/Vout), and the second terminalis coupled to the node N910. The first terminal of switch S904 iscoupled to the first voltage input (Vin/Vout), and the second terminalis coupled to the node N912. The first terminal of switch S906 iscoupled to the voltage supply node, and the second terminal is coupledto the node N914. The first terminal of switch S908 is coupled to thevoltage supply node, and the second terminal is coupled to the nodeN916. The first terminal of switch S910 is coupled to the voltage supplynode, and the second terminal is coupled to the node N906. The firstterminal of switch S938 is coupled to the node N908, and the secondterminal is coupled to the output of the operational amplifier 902 atthe node N904. The first terminal of switch S940 is coupled to the nodeN906, and the second terminal is coupled to the non-inverting input ofthe operational amplifier 902 at the node N902. The first terminal ofswitch S912 is coupled to the output (Vout), and the second terminal iscoupled to the node N910. The first terminal of switch S916 is coupledto the voltage supply node, and the second terminal is coupled to thenode N910. The first terminal of switch S918 is coupled to the secondvoltage input (vref), and the second terminal is coupled to the nodeN910. The first terminal of switch S920 is coupled to the voltage supplynode, and the second terminal is coupled to the node N912. The firstterminal of switch S922 is coupled to the third voltage input (−vref),and the second terminal is coupled to the node N912. The first terminalof switch S924 is coupled to the second voltage input (vref), and thesecond terminal is coupled to the node N912. The first terminal ofswitch S926 is coupled to the third voltage input (−vref), and thesecond terminal is coupled to the node N914. The first terminal ofswitch S928 is coupled to the voltage supply node, and the secondterminal is coupled to the node N914. The first terminal of switch S930is coupled to the second voltage input (vref), and the second terminalis coupled to the node N914. The first terminal of switch S932 iscoupled to the third voltage input (−vref), and the second terminal iscoupled to the node N916. The first terminal of switch S934 is coupledto the voltage supply node, and the second terminal is coupled to thenode N916. The first terminal of switch S936 is coupled to the secondvoltage input (vref), and the second terminal is coupled to the nodeN916.

Each of the plurality of coupled switches is further labeled by theirrespective governing clock signal (p1 or p2) or control signal (h, m, orl) that controls the opening and closing of the switch. Duringoperation, when a clock or control signal is “high”, the associatedswitch is closed; and when a clock or control signal is “low”, theassociated switch is open. More specifically, the first set of switchesS900-S910 (also referred to herein as sampling control switches) isgoverned by a sampling control clock signal p1. The second set ofswitches S912-S940 (also referred to herein as gain control switches) isgoverned by a gain control clock signal p2. In addition, the gaincontrol switches may be labeled with an “S”, “D”, or an “R”. Moreparticularly, a gain control switch labeled with only an “S” iscontrolled to close only when the control signal C_(S) (FIG. 12) is highand is used only when operating on a single ended input voltage. A gaincontrol switch labeled with only a “D” is controlled to close only whenthe control signal C_(D) (FIG. 12) is high and is used only whenoperating on a differential input voltage. A gain control switch labeledwith only an “R” is controlled to close only when the control signalC_(D) (FIG. 12) is high and is used only when operating on a residueinput voltage. A gain control switch labeled with a combination of an“S”, “D” and/or “R” is used when operating either on a single ended, adifferential or a residue input voltage, depending on the particularcontrol signal (h, m, l) applied to the switch. A gain control switchhaving no “5”, “D” or “R” is used during all residue calculation cycles.

Moreover, the subset (S920-S936) of the switches is governed by controlsignals h, m, and l as follows. Switch S920 is controlled to close bycontrol signal l when operating on a single ended signal and by acontrol signal m when operating on a residue signal. Switch S922 iscontrolled to close by control signal l when operating on a residuesignal. Switch S924 is controlled to close by control signal h whenoperating on a single ended signal or residue signal and by a controlsignal m when operating on a single ended signal. Switch S926 iscontrolled to close by control signal l when operating on a differentialsignal. Switch S928 is controlled to close by control signal m whenoperating a either single ended or differential and by control signal lwhen operating on a single ended signal. Switch S930 is controlled toclose by control signal h when operating on either a single ended ordifferential signal. Switch S932 is controlled to close by controlsignal l when operating on a differential signal. Switch S934 iscontrolled to close by control signal m when operating on either asingle ended or differential signal and by control signals l or h whenoperating on a single ended signal. Switch S936 is controlled to closeby a control signal h when operating on a differential signal.

During operation as an initial ADC stage, circuit 920 functions as doesthe circuit 820 of FIG. 8, as described above and not repeated here forthe sake of brevity. During operation after the initial residuecalculation cycle, the first set of switches (S900-S910) is configuredto close under the control of the sampling control clock signal p1during the sample cycle to charge the capacitors 904-908 in order tosample a residue input voltage (either V_(out1) or V_(out2)) at thefirst voltage input (Vin/Vout), thereby generating a residue inputvoltage sample. Upon the conclusion of the sample cycle when controlsignal p1 controls the first set of switches to open, the second set ofswitches (S912-S940) is configured to selectively close under thecontrol of the gain control clock signal p2 and one or more controlsignals (h, m, l, or C_(R)) to generate an output residue voltage basedon the comparison of the magnitude of the unscaled input voltage to thefirst upper and lower residue voltage trip points (e.g., as shown indiagram 1020 of FIG. 10). The magnitude of the output residue voltage isdetermined in accordance with the following equations: when Vin>Vh,Vout=2Vin−vref; when Vh>Vin>Vl, Vout=2Vin; and when Vin<Vl,Vout=2Vin+vref, wherein Vin is the magnitude of the residue inputvoltage, Vout is the magnitude of the output residue voltage, vref is amagnitude of the reference voltage, Vh is the upper residue voltage trippoint, and Vl is the lower residue voltage trip point.

Turning to FIG. 11, illustrated therein is a flow diagram of a method1100 implemented in an ADC stage, in accordance with an embodiment.Method 1100 is performed, for example, by components of the initial ADCstages illustrated in FIG. 1 to FIG. 4 and FIG. 6 to FIG. 9. Where theADC is configured as a pipelined ADC, the initial ADC performs onlyfunctions 1102-1108 of method 1100. When the ADC is configured as acyclic ADC, the initial ADC performs the entire method 1100. Inaccordance with method 1100, a comparator and logic circuit of aninitial ADC stage receives (1102) an unscaled input voltage having amagnitude and compares (1104) the magnitude of the unscaled inputvoltage to first upper and lower unscaled voltage trip points togenerate an initial output bit corresponding to the magnitude of theunscaled input voltage, and to generate a voltage scaling and gaincontrol signal for use in an initial residue calculation cycle of theplurality of residue calculation cycles, wherein the first upper andlower unscaled voltage trip points are different than upper and lowerresidue voltage trip points for use during the remainder of theplurality of residue calculation cycles. The initial ADC stage samples(1106) the unscaled input voltage using a set of sampling controlswitches and capacitors of a switched capacitor circuit within theinitial ADC stage and selectively closes (1108) a set of gain controlswitches of the switched capacitor circuit, under the control of thevoltage scaling and gain control signal, in order to scale the unscaledinput voltage sample and generate an initial residue voltage during theinitial residue calculation cycle.

In a further embodiment, the comparator and logic circuit of the initialADC receives (1102) a reference voltage and selectively closes (1108)the set of gain control switches, under the control of the voltagescaling and gain control signal, in order to scale the reference voltagewhile scaling the unscaled input voltage sample and generating theinitial residue voltage during the initial residue calculation cycle.Moreover, the method 1100 can be implemented for single ended ordifferential input signals. Accordingly, the first upper and lowerunscaled voltage trip points have first upper and lower values when theunscaled input voltage comprises a single ended input voltage and havedifferent upper and lower values when the unscaled input voltagecomprises a differential input voltage.

In yet a further embodiment of the method 1100, an ADC stage isconfigurable after the initial residue calculation cycle to calculate aresidue voltage without scaling the input signal. Upon beingreconfigured, the comparator and logic circuit receives (1110) a residuevoltage having a magnitude at a voltage input of the ADC stage, andcompares (1112) the magnitude of the received residue voltage to theupper and lower residue voltage trip points to generate a next outputbit corresponding to the magnitude of the received residue voltage, andto generate a gain control signal for use in a next residue calculationcycle of the plurality of residue calculation cycles. The switchedcapacitor circuit samples (1114) the residue voltage using the set ofsampling control switches and capacitors of the switched capacitorcircuit and selectively closes (1116) the set of gain control switchesof the switched capacitor circuit, under the control of the gain controlsignal, in order to generate a next residue voltage during the nextresidue calculation cycle. At 1118, if gain control signal of theswitched capacitor circuit are receiving the control signal C_(S) orC_(D), the ADC stage is configured to receive the unscaled input voltageand the method returns to block 1102. Otherwise, the method returns toblock 1110.

In the foregoing specification, specific embodiments have beendescribed. However, one of ordinary skill in the art appreciates thatvarious modifications and changes can be made without departing from thescope of the invention as set forth in the claims below. Accordingly,the specification and figures are to be regarded in an illustrativerather than a restrictive sense, and all such modifications are intendedto be included within the scope of present teachings.

The benefits, advantages, solutions to problems, and any element(s) thatmay cause any benefit, advantage, or solution to occur or become morepronounced are not to be construed as a critical, required, or essentialfeatures or elements of any or all the claims. The invention is definedsolely by the appended claims including any amendments made during thependency of this application and all equivalents of those claims asissued.

Moreover in this document, relational terms such as first and second,top and bottom, and the like may be used solely to distinguish oneentity or action from another entity or action without necessarilyrequiring or implying any actual such relationship or order between suchentities or actions. The terms “comprises,” “comprising,” “has”,“having,” “includes”, “including,” “contains”, “containing” or any othervariation thereof, are intended to cover a non-exclusive inclusion, suchthat a process, method, article, or apparatus that comprises, has,includes, contains a list of elements does not include only thoseelements but may include other elements not expressly listed or inherentto such process, method, article, or apparatus. An element proceeded by“comprises . . . a”, “has . . . a”, “includes . . . a”, “contains . . .a” does not, without more constraints, preclude the existence ofadditional identical elements in the process, method, article, orapparatus that comprises, has, includes, contains the element. The terms“a” and “an” are defined as one or more unless explicitly statedotherwise herein. The terms “substantially”, “essentially”,“approximately”, “about” or any other version thereof, are defined asbeing close to as understood by one of ordinary skill in the art, and inone non-limiting embodiment the term is defined to be within 10%, inanother embodiment within 5%, in another embodiment within 1% and inanother embodiment within 0.5%.

As used herein, the terms “configured to”, “configured with”, “arrangedto”, “arranged with”, “capable of” and any like or similar terms meanthat referenced circuit elements have an internal physical arrangement(such as by virtue of a particular transistor technology used) and/orphysical coupling and/or connectivity with other circuit elements in aninactive state. This physical arrangement and/or physical couplingand/or connectivity (while in the inactive state) enables the circuitelements to perform stated functionality while in the active state ofreceiving and processing various signals at inputs of the circuitelements to generate signals at the output of the circuit elements. Adevice or structure that is “configured” in a certain way is configuredin at least that way, but may also be configured in ways that are notlisted.

As used herein, a “node” means any internal or external reference point,connection point, junction, signal line, conductive element, or thelike, at which a given signal, logic level, voltage, data pattern,current, or quantity is present. Furthermore, two or more nodes may berealized by one physical element (and two or more signals can bemultiplexed, modulated, or otherwise distinguished even though receivedor output at a common node).

The above description refers to nodes or features being “connected” or“coupled” together. As used here and, unless expressly stated otherwise,“coupled” means that one node or feature is directly or indirectlyjoined to (or is in direct or indirect communication with) another nodeor feature, and not necessarily physically. As used herein, unlessexpressly stated otherwise, “connected” means that one node or featureis directly joined to (or is in direct communication with) another nodeor feature. For example, a switch may be “coupled” to a plurality ofnodes, but all of those nodes need not always be “connected” to eachother; moreover, the switch may connect different nodes to each otherdepending on the state of the switch. Furthermore, although the variouscircuit schematics shown herein depict certain example arrangement ofelements, additional intervening elements, devices, features, orcomponents may be present in an actual embodiment (assuming that thefunctionality of the given circuit is not adversely affected).

The Abstract of the Disclosure is provided to allow the reader toquickly ascertain the nature of the technical disclosure. It issubmitted with the understanding that it will not be used to interpretor limit the scope or meaning of the claims. In addition, in theforegoing Detailed Description, it can be seen that various features aregrouped together in various embodiments for the purpose of streamliningthe disclosure. This method of disclosure is not to be interpreted asreflecting an intention that the claimed embodiments require morefeatures than are expressly recited in each claim. Rather, as thefollowing claims reflect, inventive subject matter lies in less than allfeatures of a single disclosed embodiment. Thus the following claims arehereby incorporated into the Detailed Description, with each claimstanding on its own as a separately claimed subject matter.

What is claimed is:
 1. An analog-to-digital converter stage comprising:a comparator and logic circuit configured with first upper and lowerunscaled voltage trip points and further configured, prior to an initialresidue calculation cycle, to compare a magnitude of an unscaled inputvoltage to the first upper and lower unscaled voltage trip points, togenerate an initial output bit corresponding to the magnitude of theunscaled input voltage, and to generate a voltage scaling and gaincontrol signal; a switched capacitor circuit coupled to the comparatorand logic circuit, the switched capacitor circuit comprising a firstvoltage input, a voltage output, and a plurality of coupled capacitorsand switches configured to sample the unscaled input voltage at thefirst voltage input to generate an unscaled input voltage sample and toreceive the voltage scaling and gain control signal for selectivelycontrolling a subset of the switches in order to scale the unscaledinput voltage sample and generate an initial residue voltage having aninitial residue magnitude at the voltage output during the initialresidue calculation cycle; a second voltage input for receiving areference voltage; a voltage supply node for receiving a common modevoltage; an operational amplifier having an inverting input coupled tothe voltage supply node and a non-inverting input and having an outputterminal coupled to the voltage output of the switched capacitorcircuit; wherein the plurality of coupled capacitors comprises fourcapacitors; wherein the plurality of coupled switches comprises a firstset of switches coupled to the first voltage input, the voltage supplynode and the four capacitors, wherein the first set of switches isconfigured to close under the control of a sampling control clock signalto charge at least a subset of the four capacitors in order to samplethe unscaled input voltage at the first voltage input; wherein aremainder of the plurality of coupled switches comprises a second set ofswitches that comprises the subset of the switches, wherein the secondset of switches is coupled to the second voltage input, the voltagesupply node, the four capacitors, and the non-inverting input and theoutput of the operational amplifier.
 2. The analog-to-digital converterstage of claim 1, wherein the comparator and logic circuit is configuredwith upper and lower residue voltage trip points that are different thanthe first upper and lower unscaled voltage trip points, and wherein thecomparator and logic circuit is configured, after the initial residuecalculation cycle, to compare a magnitude of a residue voltage at thefirst voltage input to the upper and lower residue voltage trip pointsto generate a next output bit and to generate a gain control signal foruse in a next residue calculation cycle.
 3. The analog-to-digitalconverter stage of claim 2, wherein the plurality of coupled capacitorsand switches is configured, after the initial residue calculation cycle,to sample the residue voltage at the first voltage input and to receivethe gain control signal for selectively controlling the subset of theswitches to generate a next residue voltage during the next residuecalculation cycle.
 4. The analog-to-digital converter stage of claim 1,wherein: the comparator and logic circuit is configured with secondupper and lower unscaled voltage trip points that are different than thefirst upper and lower unscaled voltage trip points; the comparator andlogic circuit is configured to compare the magnitude of the unscaledinput voltage to the first upper and lower unscaled voltage trip pointsto generate the initial output bit and the voltage scaling and gaincontrol signal when the unscaled input voltage comprises a single endedinput voltage; the comparator and logic circuit is configured to comparethe magnitude of the unscaled input voltage to the second upper andlower unscaled voltage trip points to generate the initial output bitand the voltage scaling and gain control signal when the unscaled inputvoltage comprises a differential input voltage.
 5. The analog-to-digitalconverter stage of claim 1, wherein the switched capacitor circuitfurther comprises a third voltage input, coupled to the second set ofswitches, for receiving a negative reference voltage.
 6. Theanalog-to-digital converter stage of claim 5: wherein the second set ofswitches is configured to selectively close under the control of a gaincontrol clock signal and the voltage scaling and gain control signal toscale the unscaled input voltage sample and generate the initial residuevoltage in accordance with the following equations, when the unscaledinput voltage comprises a single ended input voltage: $\begin{matrix}\begin{matrix}\underset{\_}{{when},{{Vin} > {Vh}}} \\{{{Vout} = {{2{Vin}} - {3{vref}}}};}\end{matrix} \\\begin{matrix}\underset{\_}{{when},{{Vh} > {Vin} > {V\; 1}}} \\{{{Vout} = {{2{Vin}} - {2{vref}}}};}\end{matrix} \\\begin{matrix}\underset{\_}{{when},{{Vin} < {V\; 1}}} \\{{{Vout} = {{2{Vin}} - {vref}}},}\end{matrix}\end{matrix}$ wherein the second set of switches is configured toselectively close under the control of the gain control clock signal andthe voltage scaling and gain control signal to scale the unscaled inputvoltage sample and generate the initial residue voltage in accordancewith the following equations, when the unscaled input voltage comprisesa differential input voltage: $\begin{matrix}\begin{matrix}\underset{\_}{{when},{{Vin} > {Vh}}} \\{{{Vout} = {{2\left( \frac{Vin}{2} \right)} - {vref}}};}\end{matrix} \\\begin{matrix}\underset{\_}{{when},{{Vh} > {Vin} > {V\; 1}}} \\{{{Vout} = {2\left( \frac{Vin}{2} \right)}};}\end{matrix} \\\begin{matrix}\underset{\_}{{when},{{Vin} < {V\; 1}}} \\{{{Vout} = {{2\left( \frac{Vin}{2} \right)} + {vref}}},}\end{matrix}\end{matrix}$ wherein Vin is the magnitude of the unscaled inputvoltage, Vout is the initial residue magnitude, vref is a magnitude ofthe reference voltage, Vh is the upper unscaled voltage trip point, andVl is the lower unscaled voltage trip point.
 7. An analog-to-digitalconverter stage comprising: a comparator and logic circuit configuredwith first upper and lower unscaled voltage trip points and furtherconfigured, prior to an initial residue calculation cycle, to compare amagnitude of an unscaled input voltage to the first upper and lowerunscaled voltage trip points, to generate an initial output bitcorresponding to the magnitude of the unscaled input voltage, and togenerate a voltage scaling and gain control signal; a switched capacitorcircuit coupled to the comparator and logic circuit, the switchedcapacitor circuit comprising first voltage input, a voltage output, anda plurality of coupled capacitors and switches configured sample theunscaled input voltage at the first voltage input to generate anunscaled input voltage sample and to receive the voltage scaling andgain control signal for selectively controlling a subset of the switchesin order to scale the unscaled input voltage sample and generate aninitial residue voltage having an initial residue magnitude at thevoltage output during the initial residue calculation cycle, wherein theswitched capacitor circuit further comprises a second voltage input,coupled to some of the switches, for receiving a reference voltage,wherein the plurality of coupled capacitors and switches is configuredto scale the reference voltage while scaling the unscaled input voltagesample and while generating the initial residue voltage during theinitial residue calculation cycle.
 8. The analog-to-digital converterstage of claim 7, wherein the switched capacitor circuit furthercomprises: a voltage supply node for receiving a common mode voltage; anoperational amplifier having an inverting input coupled to the voltagesupply node and a non-inverting input and having an output terminalcoupled to the voltage output of the switched capacitor circuit; whereinthe plurality of coupled capacitors comprises four capacitors; whereinthe plurality of coupled switches comprises a first set of switchescoupled to the first voltage input, the voltage supply node and thecapacitors, wherein the first set of switches is configured to closeunder the control of a sampling control clock signal to charge at leasta subset of the capacitors in order to sample the unscaled input voltageat the first voltage input; wherein a remainder of the plurality ofcoupled switches comprises a second set of switches that comprises thesubset of the switches, wherein the second set of switches is coupled tothe second voltage input, the voltage supply node, the capacitors, andthe non-inverting input and the output of the operational amplifier. 9.The analog-to-digital converter stage of claim 8: wherein the switchedcapacitor circuit further comprises a third voltage input, coupled tothe second set of switches, for receiving a negative reference voltage;wherein the plurality of coupled capacitors comprises a fifth capacitorcoupled to the first and second sets of switches.
 10. Theanalog-to-digital converter stage of claim 9: wherein the second set ofswitches is configured to selectively close under the control of a gaincontrol clock signal and the voltage scaling and gain control signal toscale the unscaled input voltage sample and the reference voltage andgenerate the initial residue voltage in accordance with the followingequations, when the unscaled input voltage comprises a single endedinput voltage: $\begin{matrix}\begin{matrix}\underset{\_}{{when},{{Vin} > {Vh}}} \\{{{Vout} = {{2\left( {{Vin} - \frac{vref}{2}} \right)} - \frac{vref}{2}}};}\end{matrix} \\\begin{matrix}\underset{\_}{{when},{{Vh} > {Vin} > {V\; 1}}} \\{{{Vout} = {2\left( {{Vin} - \frac{vref}{2}} \right)}};}\end{matrix} \\\begin{matrix}\underset{\_}{{when},{{Vin} < {V\; 1}}} \\{{{Vout} = {{2\left( {{Vin} - \frac{vref}{2}} \right)} + \frac{vref}{2}}},}\end{matrix}\end{matrix}$ wherein the second set of switches is configured toselectively close under the control of the gain control clock signal andthe voltage scaling and gain control signal to scale the unscaled inputvoltage sample and the reference voltage and generate the initialresidue voltage in accordance with the following equations, when theunscaled input voltage comprises a differential input voltage:$\begin{matrix}\begin{matrix}\underset{\_}{{when},{{Vin} > {Vh}}} \\{{{Vout} = {{2\left( \frac{Vin}{2} \right)} - {vref}}};}\end{matrix} \\\begin{matrix}\underset{\_}{{when},{{Vh} > {Vin} > {V\; 1}}} \\{{{Vout} = {2\left( \frac{Vin}{2} \right)}};}\end{matrix} \\\begin{matrix}\underset{\_}{{when},{{Vin} < {V\; 1}}} \\{{{Vout} = {{2\left( \frac{Vin}{2} \right)} + \frac{vref}{2}}},}\end{matrix}\end{matrix}$ wherein Vin is the magnitude of the unscaled inputvoltage, Vout is the initial residue magnitude, vref is a magnitude ofthe reference voltage, Vh is the upper unscaled voltage trip point, andVl is the lower unscaled voltage trip point.
 11. A method for use in ananalog-to-digital conversion process comprising a plurality of residuecalculation cycles, the method comprising: receiving an unscaled inputvoltage, having a magnitude, into a comparator and logic circuitconfigured with first upper and lower unscaled voltage trip points andinto a first voltage input of a switched capacitor circuit within ananalog-to-digital converter stage, wherein the switched capacitorcircuit also has a second voltage input and a voltage output; comparingthe magnitude of the unscaled input voltage to the first upper and lowerunscaled voltage trip points to generate an initial output bitcorresponding to the magnitude of the unscaled input voltage and togenerate a voltage scaling and gain control signal for use in an initialresidue calculation cycle of the plurality of residue calculationcycles; sampling the unscaled input voltage using a set of samplingcontrol switches and capacitors of the switched capacitor circuit;selectively closing a set of gain control switches of the switchedcapacitor circuit, under the control of the voltage scaling and gaincontrol signal, in order to scale the unscaled input voltage sample andgenerate an initial residue voltage at the voltage output during theinitial residue calculation cycle; receiving a reference voltage into asecond voltage input; selectively closing the set of gain controlswitches, under the control of the voltage scaling and gain controlsignal, in order to scale the reference voltage while scaling theunscaled input voltage sample and generating the initial residue voltageduring the initial residue calculation cycle.
 12. The method of claim 11further comprising: receiving a negative reference voltage into a thirdvoltage input of the switched capacitor network, wherein the negativereference voltage is used to generate the initial residue voltage. 13.The method of claim 12 comprising: receiving a residue voltage having amagnitude at a voltage input of the switched capacitor circuit;comparing the magnitude of the residue voltage at the voltage input tothe upper and lower residue voltage trip points to generate a nextoutput bit corresponding to the magnitude of the residue voltage at thevoltage input and to generate a gain control signal for use in a nextresidue calculation cycle of the plurality of residue calculationcycles; sampling the residue voltage at the voltage input using the setof sampling control switches and capacitors of the switched capacitorcircuit; selectively closing the set of gain control switches of theswitched capacitor circuit, under the control of the gain controlsignal, in order to generate a next residue voltage during the nextresidue calculation cycle.
 14. The method of claim 11, wherein the firstupper and lower unscaled voltage trip points are different than upperand lower residue voltage trip points for use during the remainder ofthe plurality of residue calculation cycles.